Subject: CVS commit: pkgsrc/cad/verilog
To: None <email@example.com>
From: Dan McMahill <firstname.lastname@example.org>
Date: 02/08/2002 03:48:32
Module Name: pkgsrc
Committed By: dmcmahill
Date: Fri Feb 8 01:48:32 UTC 2002
pkgsrc/cad/verilog: Makefile PLIST distinfo
update to verilog-0.6
WHAT'S NEW SINCE 0.5?
Quite a lot. Innumerable bugs have been fixed, and standards coverage
has been improved significantly. Warning and error messages have been
improved, and so has compile performance. Gate delays, strength
modeling, and floating point delays have all improved since the 0.5
release. If you had trouble with the 0.5 release, the 0.6 release
probably fixes your problem.
Support for large designs spanning multiple files has been improved
dramatically. The usual preprocessor inclusion method still works, but
The 0.6 release adds command files for keeping source file lists, and
automatic library searches for missing modules. The library mechinisms
are compatible with commercial tools, and commercial module libraries
can be used with Icarus Verilog.
Many compiler limitations related to the size and complexity of large
designs have been relaxed or eliminated. There are no known design
size limitations remaining in the compiler. Icarus Verilog should be
able to handle any design that you have the patience to compile.
To generate a diff of this commit:
cvs rdiff -r1.11 -r1.12 pkgsrc/cad/verilog/Makefile
cvs rdiff -r1.1 -r1.2 pkgsrc/cad/verilog/PLIST
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/verilog/distinfo
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.