Subject: CVS commit: pkgsrc/cad/verilog-current
To: None <email@example.com>
From: Dan McMahill <firstname.lastname@example.org>
Date: 01/16/2002 21:33:19
Module Name: pkgsrc
Committed By: dmcmahill
Date: Wed Jan 16 19:33:19 UTC 2002
pkgsrc/cad/verilog-current: Makefile distinfo
update to verilog-current-20020112
many many changes since the last packaged snapshot.
A brief sampling of the changes (which include many bug fixes and
A variety of little problems with $display format strings have been
The % operand should now simulate properly. Also, the * operator is a
little bit more optimized, and works in constant expressions.
Several bugs in strength modeling have been fixed. This includes drive
strengths on continuous assignments, which in the past generated code
without the strengths. Also, vvp gained some missing support for
constants with strength. I think that strength modeling is now
vpi_get_vlog_info support has been added to the vvp run-time. This is
a PLI function that allows access to run-time command flags. Also, vpi
access to root modules now works properly.
To generate a diff of this commit:
cvs rdiff -r1.23 -r1.24 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.7 -r1.8 pkgsrc/cad/verilog-current/distinfo
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.