Subject: CVS commit: pkgsrc/cad/verilog-current
To: None <email@example.com>
From: Dan McMahill <firstname.lastname@example.org>
Date: 10/24/2001 15:27:12
Module Name: pkgsrc
Committed By: dmcmahill
Date: Wed Oct 24 12:27:12 UTC 2001
pkgsrc/cad/verilog-current: Makefile distinfo
update to verilog-current-20011020.
changes since last snapshot include:
- addition of a fpga target for synthesis. outputs edif, optimized for
xilinx virtex parts.
- fixed bug with synthesis of !=
- fixed bug in hex constant parsing
- fixed vvp bug with subtracting very wide words
- much improved VCD output
- many other bug fixes and robustness improvements.
To generate a diff of this commit:
cvs rdiff -r1.21 -r1.22 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.5 -r1.6 pkgsrc/cad/verilog-current/distinfo
cvs rdiff -r1.9 -r1.10 pkgsrc/cad/verilog-current/pkg/PLIST
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.