Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Tue Jul  3 18:23:47 UTC 2001

Modified Files:
	pkgsrc/cad/verilog-current: Makefile distinfo
	pkgsrc/cad/verilog-current/pkg: PLIST
Removed Files:
	pkgsrc/cad/verilog-current/patches: patch-aa patch-ab

Log Message:
update to 20010630 snapshot.

changes are:
-----------
RELEASE NOTE FOR ICARUS VERILOG 20010630

I've done some cleanup of the mingw port of Icarus Verilog. I've also
added instructions for how to build Icarus Verilog under mingw. I'm
working on making that the preferred way to support Windows, and when
I make the 0.5 release I will make Windows binaries this way. Anyhow,
feedback on the build instructions and the build results using the
instructions in mingw.txt are welcome.

I've make "vvp" the default target type. The older vvm behavior is
available with the "-tvvm" flag to iverilog, but I would rather be
told about (and fix) bugs in the vvp code generator and run time.

I've added support for the (unsigned) right shift operator. The left
shift has been working for a while now, but right shift somehow
slipped through the cracks. The shift operators still don't quite work
in structural contexts, but they should show up sometime next week.

I've finally got VCD output working properly with vvp. It may even be
better then with vvm, although some internal symbols are still generated.

A few odd bugs have been fixed, including a code generation error for
xnf, and error checking of user defined function parameters.


To generate a diff of this commit:
cvs rdiff -r1.19 -r1.20 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.4 -r1.5 pkgsrc/cad/verilog-current/distinfo
cvs rdiff -r1.8 -r0 pkgsrc/cad/verilog-current/patches/patch-aa
cvs rdiff -r1.5 -r0 pkgsrc/cad/verilog-current/patches/patch-ab
cvs rdiff -r1.8 -r1.9 pkgsrc/cad/verilog-current/pkg/PLIST

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.