Subject: CVS commit: pkgsrc
To: None <firstname.lastname@example.org>
From: Dan McMahill <email@example.com>
Date: 03/31/2001 03:00:36
Module Name: pkgsrc
Committed By: dmcmahill
Date: Sat Mar 31 00:00:36 UTC 2001
pkgsrc/cad/verilog-current/files: md5 patch-sum
pkgsrc/cad/verilog-current/patches: patch-ab patch-ac patch-ae patch-af
update to verilog-current-20010324. Changes since the last version from
the authors announcement are:
There are a few bugs in the main compiler that are fixed. There has
also been an extension to the $fopen that adds support for opening
files for reading. The $fgetc has been added to take advantage of this.
This was done on the VPI side, although a slight extension to the mcd
functions was created.
The real news is the vvp simulation engine. I've added the tgt-vvp
code generator source and the vvp assembler/simulator, and the combination
actually produces the occasional working program. And it makes them
very quickly. So far as I can tell now, I am going to be very pleased
with the final outcome when this work is complete. However, it is not
at all ready to use. This snapshot is mostly to give a preview of things
to come to a wider audience.
HOW VVP WORKS
If you are accustomed to the existing vvm behavior, you remember that
the vvm simulator works by generating C++ and feeding that to the g++
compiler. Many of you are painfully aware of that.
VVP does *not* work like that. Instead of generating C++, the
generator emits assembly language for an abstract simulator processor.
The processor that the assembly targets doesn't really exist, but the
vvp program, included in this Icarus Verilog snapshot, assembles the
code to data structures in memory, then efficiently emulates the abstract
So the simulation of a program via vvp works by first compiling the
Verilog to vvp assembly. The vvp.tgt modules generates the code, and
is envoked when you use the ``-tvvp'' switch to iverilog.
The vvp assembly file so created is then passed to the vvp program to
be assembled and executed. There is a single vvp input file that is the
design to simulate. The vvp assembler is designed to execute the design
HOW TO LEARN MORE
The ivl_target.h header file describes the loadable target API that
the vvp code generator uses to gain access to the design. Then the
tgt-vvp directory contains the implementation of the vvp code generator.
The vvp directory contains the implementation of the assembler/simulator
that runs the compiled design. The README.txt file describes how the
vvp program works in general, and points to other txt files. There are
a variety of other .txt files in the vvp directory that describe how
the major components of the vvp program work.
To generate a diff of this commit:
cvs rdiff -r1.13 -r1.14 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.11 -r1.12 pkgsrc/cad/verilog-current/files/md5
cvs rdiff -r1.10 -r1.11 pkgsrc/cad/verilog-current/files/patch-sum
cvs rdiff -r1.5 -r1.6 pkgsrc/cad/verilog-current/patches/patch-aa
cvs rdiff -r0 -r1.3 pkgsrc/cad/verilog-current/patches/patch-ab \
cvs rdiff -r0 -r1.1 pkgsrc/cad/verilog-current/patches/patch-ac \
cvs rdiff -r1.7 -r1.8 pkgsrc/cad/verilog-current/pkg/PLIST
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.