[pkgsrc/trunk]: pkgsrc/cad/MyHDL-iverilog import MyHDL-iverilog-0.5, an Icaru...

[drochner <drochner%pkgsrc.org@localhost>]

details:   https://anonhg.NetBSD.org/pkgsrc/rev/1eb4f9540db0
branches:  trunk
changeset: 507874:1eb4f9540db0
user:      drochner <drochner%pkgsrc.org@localhost>
date:      Fri Feb 10 17:05:03 2006 +0000

description:
import MyHDL-iverilog-0.5, an Icarus Verilog vpi module to support cosimulation
from py-MyHDL

diffstat:

 cad/MyHDL-iverilog/DESCR    |   7 +++++++
 cad/MyHDL-iverilog/Makefile |  20 ++++++++++++++++++++
 cad/MyHDL-iverilog/PLIST    |   2 ++
 cad/MyHDL-iverilog/distinfo |   5 +++++
 4 files changed, 34 insertions(+), 0 deletions(-)

diffs (50 lines):

diff -r 36905e2c488e -r 1eb4f9540db0 cad/MyHDL-iverilog/DESCR
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/MyHDL-iverilog/DESCR  Fri Feb 10 17:05:03 2006 +0000
@@ -0,0 +1,7 @@
+MyHDL is a Python package for using Python as a hardware
+description language. Popular hardware description languages, like
+Verilog and VHDL, are compiled languages. MyHDL with Python
+can be viewed as a "scripting language" counterpart of such
+languages. However, Python is more accurately described as a very
+high level language (VHLL). MyHDL users have access to the
+amazing power and elegance of Python for their modeling work.
diff -r 36905e2c488e -r 1eb4f9540db0 cad/MyHDL-iverilog/Makefile
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/MyHDL-iverilog/Makefile       Fri Feb 10 17:05:03 2006 +0000
@@ -0,0 +1,20 @@
+# $NetBSD: Makefile,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $
+#
+
+DISTNAME=      myhdl-0.5
+PKGNAME=       MyHDL-iverilog-0.5
+CATEGORIES=    cad python
+MASTER_SITES=  ${MASTER_SITE_SOURCEFORGE:=myhdl/}
+
+MAINTAINER=    tech-pkg%NetBSD.org@localhost
+HOMEPAGE=      http://jandecaluwe.com/Tools/MyHDL/Overview.html
+COMMENT=       Icarus Verilog cosimulation support for py-MyHDL
+
+BUILD_DIRS+=   cosimulation/icarus
+
+do-install:
+       ${INSTALL_DATA} ${WRKSRC}/cosimulation/icarus/myhdl.vpi \
+               ${PREFIX}/lib/ivl
+
+.include "../../cad/verilog/buildlink3.mk"
+.include "../../mk/bsd.pkg.mk"
diff -r 36905e2c488e -r 1eb4f9540db0 cad/MyHDL-iverilog/PLIST
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/MyHDL-iverilog/PLIST  Fri Feb 10 17:05:03 2006 +0000
@@ -0,0 +1,2 @@
+@comment $NetBSD: PLIST,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $
+lib/ivl/myhdl.vpi
diff -r 36905e2c488e -r 1eb4f9540db0 cad/MyHDL-iverilog/distinfo
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/MyHDL-iverilog/distinfo       Fri Feb 10 17:05:03 2006 +0000
@@ -0,0 +1,5 @@
+$NetBSD: distinfo,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $
+
+SHA1 (myhdl-0.5.tar.gz) = c97517d7b70d6e4a56f6a2576baa685d53c394d3
+RMD160 (myhdl-0.5.tar.gz) = 2cbc89c5c2bd61a636b64bf5654471900f940ffc
+Size (myhdl-0.5.tar.gz) = 759071 bytes