[pkgsrc/trunk]: pkgsrc/cad/verilog update to verilog-0.8.3

[dmcmahill <dmcmahill%pkgsrc.org@localhost>]

details:   https://anonhg.NetBSD.org/pkgsrc/rev/b773bd2e70c5
branches:  trunk
changeset: 519533:b773bd2e70c5
user:      dmcmahill <dmcmahill%pkgsrc.org@localhost>
date:      Wed Oct 04 23:52:47 2006 +0000

description:
update to verilog-0.8.3

** Release Notes for Icarus Verilog 0.8.3

This is a new release of the stable 0.8 branch. The changes from 0.8.2
are intended to be evolutionary, rather then revolutionary, to enhance
the stability of the branch.

Various simulator bugs have been fixed, including (but not limited to):
- Detect overrun of timescale vs. precision
- Handle more operators in constant expressions
- Various ivl crashes and panics fixed.
- Some performance bottlenecks have been fixed.
- Various tool compilation problems have been fixed.

Also, the internal synthesizer (for synthesis targets) has been
considerably improved. NOTE that the code generators have not been
improved to take advantage of all the changes here, so there is work
yet to be done.

The mingw build process for compiling in Windows has been reworked. It
is now possible (indeed preferable) to compile fully native Icarus
Verilog binaries on Windows with no Cygwin tools at all.

diffstat:

 cad/verilog/Makefile         |   4 ++--
 cad/verilog/distinfo         |  10 +++++-----
 cad/verilog/patches/patch-ad |  19 ++++++++++---------
 3 files changed, 17 insertions(+), 16 deletions(-)

diffs (64 lines):

diff -r 44feb7e000f1 -r b773bd2e70c5 cad/verilog/Makefile
--- a/cad/verilog/Makefile      Wed Oct 04 22:40:40 2006 +0000
+++ b/cad/verilog/Makefile      Wed Oct 04 23:52:47 2006 +0000
@@ -1,7 +1,7 @@
-# $NetBSD: Makefile,v 1.29 2006/05/28 17:31:26 rillig Exp $
+# $NetBSD: Makefile,v 1.30 2006/10/04 23:52:47 dmcmahill Exp $
 #
 
-DISTNAME=      verilog-0.8.2
+DISTNAME=      verilog-0.8.3
 CATEGORIES=    cad
 MASTER_SITES=  ftp://icarus.com/pub/eda/verilog/v0.8/
 
diff -r 44feb7e000f1 -r b773bd2e70c5 cad/verilog/distinfo
--- a/cad/verilog/distinfo      Wed Oct 04 22:40:40 2006 +0000
+++ b/cad/verilog/distinfo      Wed Oct 04 23:52:47 2006 +0000
@@ -1,6 +1,6 @@
-$NetBSD: distinfo,v 1.10 2006/05/06 19:13:55 dmcmahill Exp $
+$NetBSD: distinfo,v 1.11 2006/10/04 23:52:47 dmcmahill Exp $
 
-SHA1 (verilog-0.8.2.tar.gz) = ab6966cf85976160c2f6974b7836336271044f71
-RMD160 (verilog-0.8.2.tar.gz) = 4e233941068d3a38f6036700614a21404e7287d4
-Size (verilog-0.8.2.tar.gz) = 1526676 bytes
-SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a
+SHA1 (verilog-0.8.3.tar.gz) = c3fd64bcdc51d44bde1fd5e168cdff761057c798
+RMD160 (verilog-0.8.3.tar.gz) = b45c7b9811f99ad833e6bf8e5508a72472b7b8f7
+Size (verilog-0.8.3.tar.gz) = 1568131 bytes
+SHA1 (patch-ad) = 41628d48a697499e71471defccb596426a098da7
diff -r 44feb7e000f1 -r b773bd2e70c5 cad/verilog/patches/patch-ad
--- a/cad/verilog/patches/patch-ad      Wed Oct 04 22:40:40 2006 +0000
+++ b/cad/verilog/patches/patch-ad      Wed Oct 04 23:52:47 2006 +0000
@@ -1,22 +1,23 @@
-$NetBSD: patch-ad,v 1.7 2004/10/14 22:29:04 dmcmahill Exp $
+$NetBSD: patch-ad,v 1.8 2006/10/04 23:52:48 dmcmahill Exp $
 
---- Makefile.in.orig   2003-06-25 03:48:39.000000000 +0200
-+++ Makefile.in        2003-07-12 19:11:41.000000000 +0200
-@@ -170,7 +170,17 @@
- 
+--- Makefile.in.orig   2006-10-04 17:08:59.000000000 +0000
++++ Makefile.in        2006-10-04 22:39:41.000000000 +0000
+@@ -171,6 +171,17 @@
  lexor.o: lexor.cc parse.h
  
+-parse.o: parse.cc
++ 
 +# work around buggy compilers when compiling the parser with optimization
 +# make sure no one sneaks a -O* in on us via one of these variables
 +# set in the environment
 +CXX_NOOPT=$(CXX:-O%=)
 +CPPFLAGS_NOOPT=$(CPPFLAGS:-O%=)
 +CXXFLAGS_NOOPT=$(CXXFLAGS:-O%=)
-+
- parse.o: parse.cc
+ 
++parse.o: parse.cc
 +      @[ -d dep ] || mkdir dep
 +      $(CXX_NOOPT) $(CPPFLAGS_NOOPT) $(CXXFLAGS_NOOPT) -MD -c $< -o $*.o
 +      mv $*.d dep/$*.d
- 
- parse.cc: $(srcdir)/parse.y
++ 
+ parse.cc parse.h: $(srcdir)/parse.y
        $(YACC) --verbose -t -p VL -d -o parse.cc $(srcdir)/parse.y