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On Aug 23, 2005, at 15:28 , Thor Lancelot Simon wrote:

> I am in the process of adding support to the "sk" driver for newer
> variants of the Marvell gigabit ethernet controller.  The only one
> of these that seems at all common is the 88E8053, which is embedded
> on many Athlon64 motherboards.
>
> However, the Linux device driver knows about a huge number of 'sk'
> chips that we don't.  In particular, there are a number of 100Mbit
> variants, and there is some specific code in the driver to support
> these.
>
> If anyone has such a device I would like to borrow it, find out where
> you got it, or at least arrange for you to test some patches.

I have two machines with ASUS K8V motherboards, which have a
skc0 at pci0 dev 10 function 0: irq 11
skc0: Marvell Yukon Lite Gigabit Ethernet rev. A3(0x7)
sk0 at skc0 port A: Ethernet address 00:11:2f:94:87:41
makphy0 at sk0 phy 0: Marvell 88E1011 Gigabit PHY, rev. 5
makphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT,  
1000baseT-FDX, auto


I had to apply the patch below to get dhclient to work on this  
interface. Looks like the PHY needs an explicit reset whenever the  
interface is reset.  See rev 1.109 in http://www.freebsd.org/cgi/ 
cvsweb.cgi/src/sys/pci/if_sk.c

The machine can be made available for testing.
-- 
     aew


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Index: if_sk.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_sk.c,v
retrieving revision 1.15
diff -u -p -u -r1.15 if_sk.c
--- if_sk.c	30 May 2005 04:35:22 -0000	1.15
+++ if_sk.c	8 Sep 2005 17:23:32 -0000
@@ -2331,11 +2331,21 @@ void sk_init_yukon(sc_if)
 {
 	u_int32_t		/*mac, */phy;
 	u_int16_t		reg;
+	struct sk_softc		*sc;
 	int			i;
 
 	DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n",
 		     CSR_READ_4(sc_if->sk_softc, SK_CSR)));
 
+	sc = sc_if->sk_softc;
+	if (sc->sk_type == SK_YUKON_LITE &&
+	    sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
+		/* Take PHY out of reset. */
+		sk_win_write_4(sc, SK_GPIO,
+			(sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9);
+	}
+
+
 	/* GMAC and GPHY Reset */
 	SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
 

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