Subject: Re: PC engine WRAP
To: None <firstname.lastname@example.org>
From: Ian Zagorskih <email@example.com>
Date: 06/20/2005 17:01:31
On Monday 20 June 2005 16:33, Jukka Salmi wrote:
> Emmanuel Dreyfus --> netbsd-users (2005-06-19 17:22:30 +0200):
> > Jukka Salmi <firstname.lastname@example.org> wrote:
> > > The attached patch works at least with -current.
> > Do you know what it is doing? (just to have something to tell in the CVS
> > commit log...)
> You should not commit the patch... The problem is the lack of a keyboard
> controller. See gateA20() in src/sys/arch/i386/stand/lib/gatea20.c: there=
> a comment saying "XXX How to check for AMD Elan SC520?". The patch just
> comments out most of the code in gateA20(), assuming the code runs on a
> SC520 only...
> So this is only a workaround until a check for SC520 is found.
AFAIU Elan SC520 understands CPUID instruction. At least according to AMD=20
IDENTIFYING THE CPU CORE
Information about the integrated Am5x86 CPU core is available by reading th=
processor DX register after a system reset and by using the CPUID instructi=
at any time. The CPUID instruction is available on later model 32-bit=20
processors from all leading x86 vendors and allows programs to determine=20
information about the CPU, including the manufacturer, cache type, and=20
availability of a floating point unit (FPU). By using the CPUID instruction=
software can determine the type of CPU running the system. For example,=20
software could detect that it is running on an Am5x86 CPU and perform the=20
The =C3=89lanSC520 Microcontroller Revision ID (REVID) register (MMCR offse=
can be used to identify the revision of the device itself.
A user-modifiable bit in the CPU=E2=80=99s Flags register called the ID bit=
support of the CPUID instruction. The ID bit is reset to 0 at CPU hard or=20
soft reset for compatibility with existing processor designs.
The results reported by the CPUID instruction reflect the state of the=20
processor at the last CPU hard or soft reset. If the CPU cache write mode o=
core clock speed is changed, and if the CPU encounters a soft reset followi=
the change, then a subsequent CPUID instruction will report the altered=20
condition of the processor (i.e., the state at the time the soft reset=20
occurred). After a hard CPU reset, the =C3=89lanSC520 microcontroller alway=
reports the cache mode as write-back and the clock speed as 100 MHz.
Also MMCR registers hold usefull info too. I have several Elan SC520 based=
boards so if you'r gonna try it i can run tests.