With the great help and thanks to Enami Tsugumoto this has been tracked down to 
the point where it is working.

I hope that he will report his finding via the proper channels, but I thought I 
would reply to this incase someone is searching this in future.

It seems the CSR for this interface replies with (among others) 0x00000400 which 
Linux has defined as INTx emulation.

With a quick patch to ask it to disable this, and use legacy PCI interrupts it 
works very well.

It is probably not recommended anyone uses the patch included, but rather fetch 
the distribution where this has been fixed properly.

Much appreciated, thank you.

Lund

Index: siside.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/siside.c,v
retrieving revision 1.13
diff -c -r1.13 siside.c
*** siside.c	21 Aug 2004 00:28:34 -0000	1.13
--- siside.c	19 Oct 2004 03:27:02 -0000
***************
*** 87,96 ****
--- 87,106 ----
   {
   	struct pci_attach_args *pa = aux;
   	struct pciide_softc *sc = (struct pciide_softc *)self;
+ 	pci_chipset_tag_t pc = pa->pa_pc;
+ 	pcitag_t tag = pa->pa_tag;
+ 	pcireg_t csr;

   	pciide_common_attach(sc, pa,
   	    pciide_lookup_product(pa->pa_id, pciide_sis_products));

+ 	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
+ 	printf("%s: CSR = %x\n",
+ 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, csr);
+ 	if (csr & 0x400) {
+ 		csr &= ~0x400;
+ 		pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
+ 	}
   }

   static struct sis_hostbr_type {



Jorgen Lundman wrote:
> 
> Having nothing better to do I thought I would enabled ATADEBUG and step 
> through the code a little so I understand it.
> 
> First we have:
> 
> siside0 at pci0 dev 2 function 5
> siside0: Silicon Integrated Systems 96X UDMA6655 IDE controller (rev. 0x01)
> siside0: bus-master DMA support present
> siside0: primary channel configured to compatibility mode
> siside0: primary channel interrupting at ioapic0 pin 14 (irq 14)
> atabus0 at siside0 channel 0
> siside0: secondary channel configured to compatibility mode
> siside0: secondary channel interrupting at ioapic0 pin 15 (irq 15)
> atabus1 at siside0 channel 1
> 
> That seems to hit
> 186: sis_chip_map
> 
> and picks it up as a SIS_TYPE_133NEW which in turn sets atac_set_modes 
> to point to sis96x_setup_channel.
> 
> Then we iterate each channel to call pciide_mapchan. That works fine 
> after all.
> 
> In contrast, when we get to:
> 
> siside1 at pci0 dev 5 function 0
> siside1: Silicon Integrated Systems 180/96X SATA controller (rev. 0x01)
> siside1: bus-master DMA support present
> siside1: primary channel wired to native-PCI mode
> siside1: using ioapic0 pin 17 (irq 11) for native-PCI interrupt
> atabus2 at siside1 channel 0
> siside1: secondary channel wired to native-PCI mode
> atabus3 at siside1 channel 1
> pdcide0 at pci0 dev 8 function 0
> 
> we end up in:
> 
> 475: sis_sata_chip_map
> 
> Similar, but simpler functions. No typproduct type checks required. Sets 
> atac_set_modes to sata_setup_channel. Then iterates channels to call 
> pciide_mapchan.
> 
> 
> Comparing sis96x_setup_channel and sata_setup_channel, there are some 
> differences (obviously)..
> 
> sis96x_setup_channel has a fair bit of timing code, (SIS_TIM133 macro) 
> with regtim) and code to set sis_tim.
> 
> sata_setup_channel has none of that, only sets idedma_ctl.
> 
> Very clean code, which unfortunately means I am unsure what could 
> possibly be wrong.
> 
> On a similar note, not related to his problem since it is code for 
> different type, but is the missing "break;" in this switch supposed to 
> be omitted?
> 
> 408:
>             switch (sc->sis_type) {
>             case SIS_TYPE_66:
>             case SIS_TYPE_100OLD:
>                 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] <<
>                     SIS_TIM66_UDMA_TIME_OFF(drive);
>                 break;
>             case SIS_TYPE_100NEW:
>                 sis_tim |=
>                     sis_udma100new_tim[drvp->UDMA_mode] <<
> ===>>>>>>                SIS_TIM100_UDMA_TIME_OFF(drive);
>             case SIS_TYPE_133OLD:
>                 sis_tim |=
>                     sis_udma133old_tim[drvp->UDMA_mode] <<
>                     SIS_TIM100_UDMA_TIME_OFF(drive);
>                 break;
>             default:
> 
> 
> 
> 
> 
> 
> With ATADEBUG/probe on:
> 
> [snip]
> siside0 at pci0 dev 2 function 5
> siside0: Silicon Integrated Systems 96X UDMA6655 IDE controller (rev. 0x01)
> siside0: bus-master DMA support present
> siside0: primary channel configured to compatibility mode
> siside0: primary channel interrupting at ioapic0 pin 14 (irq 14)
> atabus0 at siside0 channel 0
> siside0: secondary channel configured to compatibility mode
> siside0: secondary channel interrupting at ioapic0 pin 15 (irq 15)
> atabus1 at siside0 channel 1
> siside0: CSR = 2100005
> [snip]
> siside1 at pci0 dev 5 function 0
> siside1: Silicon Integrated Systems 180/96X SATA controller (rev. 0x01)
> siside1: bus-master DMA support present
> siside1: primary channel wired to native-PCI mode
> siside1: using ioapic0 pin 17 (irq 11) for native-PCI interrupt
> atabus2 at siside1 channel 0
> siside1: secondary channel wired to native-PCI mode
> atabus3 at siside1 channel 1
> siside1: CSR = 2200405
> [snip]
> 
> 
> Kernelized RAIDframe activated
> siside0:0: before reset, st0=0x50, st1=0x50
> siside0:1: before reset, st0=0x50, st1=0x50
> siside1:0: before reset, st0=0x50, st1=0x0
> siside1:1: before reset, st0=0x50, st1=0x0
> siside0:1:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside0:1:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside0:1: wdcwait_reset() end, st0=0x50 st1=0x50
> siside0:1: after reset, ret_value=0x3
> siside0:1:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside0:1:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside0:1: wait DRDY st0 0x50 st1 0x50
> atabusattach: ch_drive_flags 0x1 0x1
> siside1:0:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside1:0:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside1:0: wdcwait_reset() end, st0=0x50 st1=0x0
> siside1:0: after reset, ret_value=0x3
> siside1:0:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside1:0:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside1:1:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside1:1:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside1:1: wdcwait_reset() end, st0=0x50 st1=0x0
> siside1:1: after reset, ret_value=0x3
> siside1:1:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside1:1:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> pdcide0:0: before reset, st0=0x50, st1=0x0
> pdcide0:0:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> pdcide0:0:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> pdcide0:0: wdcwait_reset() end, st0=0x50 st1=0x0
> pdcide0:0: after reset, ret_value=0x3
> pdcide0:0:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> pdcide0:0:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> pdcide0:1: before reset, st0=0x20, st1=0x30
> pdcide0:1 drive 0 wd_cyl_lo(2): got 0x2 != 0x01
> pdcide0:1 drive 1 wd_cyl_lo(2): got 0x2 != 0x01
> atabusattach: ch_drive_flags 0x0 0x0
> siside0:0:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside0:0:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside0:0: wdcwait_reset() end, st0=0x50 st1=0x50
> siside0:0: after reset, ret_value=0x3
> siside0:0:0: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside0:0:1: after reset, sc=0x1 sn=0x1 cl=0x0 ch=0x0
> siside0:0: wait DRDY st0 0x50 st1 0x50
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x0 bits 0x0)
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x0 bits 0x0)
> atabusattach: ch_drive_flags 0x1 0x1
> wd0 at atabus0 drive 0: <ST310211A>
> wd0: drive supports 16-sector PIO transfers, LBA addressing
> wd0: 9541 MB, 19386 cyl, 16 head, 63 sec, 512 bytes/sect x 19541088 sectors
> wd0: 32-bit data port
> wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
> wd1 at atabus0 drive 1: <Maxtor 4G120J6>
> wd1: drive supports 16-sector PIO transfers, LBA48 addressing
> wd1: 114 GB, 238216 cyl, 16 head, 63 sec, 512 bytes/sect x 240121728 
> sectors
> wd1: 32-bit data port
> wd1: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
> wd0(siside0:0:0): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (using 
> DMA data
>  transfers)
> wd1(siside0:0:1): using PIO mode 4, Ultra-DMA mode 6 (Ultra/133) (using 
> DMA data
>  transfers)
> wd2 at atabus1 drive 0: <Maxtor 4D080H4>
> wd2: drive supports 16-sector PIO transfers, LBA48 addressing
> wd2: 78167 MB, 158816 cyl, 16 head, 63 sec, 512 bytes/sect x 160086528 
> sectors
> wd2: 32-bit data port
> wd2: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
> wd3 at atabus1 drive 1: <Maxtor 6Y160P0>
> wd3: drive supports 16-sector PIO transfers, LBA48 addressing
> wd3: 152 GB, 317632 cyl, 16 head, 63 sec, 512 bytes/sect x 320173056 
> sectors
> wd3: 32-bit data port
> wd3: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
> wd2(siside0:1:0): using PIO mode 4, Ultra-DMA mode 6 (Ultra/133) (using 
> DMA data
>  transfers)
> wd3(siside0:1:1): using PIO mode 4, Ultra-DMA mode 6 (Ultra/133) (using 
> DMA data
>  transfers)
> siside1:0: wait DRDY st0 0x50 st1 0x0
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x0 bits 0x0)
> atabusattach: ch_drive_flags 0x1 0x0
> wd4 at atabus2 drive 0siside1:1: wait DRDY st0 0x50 st1 0x0
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x0 bits 0x0)
> atabusattach: ch_drive_flags 0x1 0x0
> pdcide0:0: wait DRDY st0 0x50 st1 0x0
> atabusattach: ch_drive_flags 0x1 0x0
> siside1:0: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> : <Maxtor 6B200M0>
> wd4: drive supports 16-sector PIO transfers, LBA48 addressing
> wd4: 189 GB, 395136 cyl, 16 head, 63 sec, 512 bytes/sect x 398297088 
> sectors
> siside1:0: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> siside1:0: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> wd4: 32-bit data port
> siside1:0: lost interrupt
>         type: ata tc_bcount: 0 tc_skip: 0
> wd4: drive supports PIO mode 4siside1:0: lost interrupt
>         type: ata tc_bcount: 0 tc_skip: 0
> , DMA mode 2siside1:0: lost interrupt
>         type: ata tc_bcount: 0 tc_skip: 0
> , Ultra-DMA mode 6 (Ultra/133)
> wd4(siside1:0:0): using PIO mode 4, Ultra-DMA mode 6 (Ultra/133) (using 
> DMA data
>  transfers)
> wd5 at atabus3 drive 0siside1:1: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> : <Maxtor 6B200M0>
> wd5: drive supports 16-sector PIO transfers, LBA48 addressing
> wd5: 189 GB, 395136 cyl, 16 head, 63 sec, 512 bytes/sect x 398297088 
> sectors
> siside1:1: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> siside1:1: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> wd5: 32-bit data port
> siside1:1: lost interrupt
>         type: ata tc_bcount: 0 tc_skip: 0
> wd5: drive supports PIO mode 4siside1:1: lost interrupt
>         type: ata tc_bcount: 0 tc_skip: 0
> , DMA mode 2siside1:1: lost interrupt
>         type: ata tc_bcount: 0 tc_skip: 0
> , Ultra-DMA mode 6 (Ultra/133)
> wd5(siside1:1:0): using PIO mode 4, Ultra-DMA mode 6 (Ultra/133) (using 
> DMA data
>  transfers)
> wd6 at atabus4 drive 0: <Maxtor 4G120J6>
> wd6: drive supports 16-sector PIO transfers, LBA48 addressing
> wd6: 114 GB, 238216 cyl, 16 head, 63 sec, 512 bytes/sect x 240121728 
> sectors
> wd6: 32-bit data port
> wd6: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
> wd6(pdcide0:0:0): using PIO mode 4, Ultra-DMA mode 6 (Ultra/133) (using 
> DMA data
>  transfers)
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x40 bits 0x40)
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x40 bits 0x40)
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x40 bits 0x40)
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x40 bits 0x40)
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x40 bits 0x40)
> siside1:0: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x40 bits 0x40)
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x40 bits 0x40)
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x40 bits 0x40)
> siside1:0: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> siside1:0: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> siside1:0: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> siside1:0: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> siside1:0: lost interrupt
>         type: ata tc_bcount: 0 tc_skip: 0
> siside1:1: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x40 bits 0x40)
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x40 bits 0x40)
> __wdcwait: timeout (time=11), status d0 error d0 (mask 0x40 bits 0x40)
> siside1:1: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> siside1:1: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> siside1:1: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> siside1:1: lost interrupt
>         type: ata tc_bcount: 512 tc_skip: 0
> siside1:1: lost interrupt
> 
> [snip]
> 
> Lund
> 
> 
> 
> 
> 

-- 
Jorgen Lundman       | <lundman@lundman.net>
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