Emre writes:
> 
> > No.  Work is being done *right now* to provide SMP on Alpha and Sparc.
> 
> Whoa...that's even better!
> If NetBSD would use all processors in my Ultra 60 I would dump buggy
> Slowaris for life.

Well, don't get too excited.  They're working on it, but Rome wasn't built
in a day.

> It kinda makes sense though.  I don't understand people that use SMP intel
> boxes (note that server was not my idea :) anyway.

Cuz we're stupid stupid stupid, and cheap cheap cheap. :-) :-)

> Heh, just curious...what's the purpose of those patches?  So are you
> saying they will only make the other processor show up on dmesg and that's
> it?

Pretty much.  
NetBSD 1.4P (LANFEAR.MP) #5: Tue Dec 14 13:50:09 EST 1999
    root:/usr/src/sys/arch/sparc/compile/LANFEAR.MP
total memory = 64788 KB
avail memory = 57960 KB
using 835 buffers containing 3340 KB of memory
bootpath: /iommu@f,e0000000/sbus@f,e0001000/espdma@f,400000/esp@f,800000/sd@3,0
mainbus0 (root): SUNW,SPARCstation-10
cpu0 at mainbus0: mid 8: TMS390Z50 v1 @ 36 MHz, on-chip FPU
cpu0: physical 20K instruction (64 b/l), 16K data (32 b/l): cache enabled
cpu1 at mainbus0: mid 10: TMS390Z50 v1 @ 36 MHz, on-chip FPU
cpu1: physical 20K instruction (64 b/l), 16K data (32 b/l): cache enabled
obio0 at mainbus0


Nice.  Even though cpu1 is doing nothing but run the idle loop (I believe),
it gives me a nice warm fuzzy feeling. :)  My dual intel box doesn't
even give me this.. :(

-Andrew
-- 
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Andrew Gillham                            | This space left blank
gillham@whirlpool.com                     | inadvertently.
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