Subject: Re: MPC860 port status
To: None <email@example.com>
From: Toru Nishimura <firstname.lastname@example.org>
Date: 04/11/2002 17:40:30
David Querbach <email@example.com> wrote;
> The MPC8xx MMU is fundamentally different from the PPC60x MMU, being much
> closer to the x86 MMU in its general design, but without hardware support
> for page modification detection.
> We started a pmap for the MPC8xx, then got dragged off to do other work. I
> believe the Plat'Home people in Japan also did a pmap, but the last time I
> checked, they still needed to add page modification emulation. I'm not sure
> what the current status of their port is.
I obtained Masanari Tsubai's code, which was handed to the Japanese company,
to inspect and learned about MPC860/850. The processor's "MMU" design
approach is pretty close to MIPS and quite distinct from the original Power
virtual memory. Generally speaking, it can not be regard a good idea to copy
i386 pmap to go since it's suffered from the accumlated feature variations of
such the processor diversity (Hi, SH3). I once toyed an idea to maintain two
4G address ranges in parallel for user and kernel, and then reluctantly
abandoned as I could not find a handy solution.