Hello NetBSD folks,

I'm trying to find some NetBSD developers interested to do a port of your
great NetBSD to OpenRISC 1000 architecture. OpenRISC 1000 architecture is a
foundation for a free, open source, scalable 32/64-bit RISC architecture.
All work is done in spirit very similar to NetBSD development - open source
development of free, open source IP cores (IP stands for intelectual
property) and OpenRISC is our processor family that works together with our
open source peripherals and system controllers (hence one would say we are
building free, open source platform).

OpenRISC 1200 is implementation of the OpenRISC 1000 architecture with the
following basic features: 32-bit scalar RISC with Harvard microarchitecture,
5 stage integer pipeline, virtual memory support (MMU) and basic DSP
capabilities. Caches are 1-4-way set-associative 1-64KB data/insn cache.
Supplemental facilities include debug unit for real-time debugging, high
resolution tick timer, programmable interrupt controller and power
management support. When implemented in a typical 0.18u 6LM process it
should provide over 400 dhrystone 2.1 MIPS at 400MHz and 400 DSP MAC 32x32
operations. Commercial competition ARM10, ARC and Tensilica RISC processors.
Beside RISC and its units we are also working for system and peripheral
controllers for our system such as memory controller, ethernet MAC, USB,
IrDA, 16550 UART, VGA/LCD controller etc. I guess we would need help with
device drivers for these controllers.

If anyone is interested to port NetBSD to OR1K and specifically to OR1200,
please have a look at:
http://www.opencores.org/cgi-bin/cvsget.cgi/or1k/docs/openrisc_arch3.pdf
(1.4MB)
http://www.opencores.org/cgi-bin/cvsget.cgi/or1k/docs/openrisc1200_spec.pdf
(450KB)

For more information about our mission, please viist us at
http://www.opencores.org. Thanks !

regards,
Damjan

PS We also have GNU toolchain for OR1K architecture. However some parts of
it are not in the official GNU tree yet (but they are available in our CVS)