Re: kern/60144: virtio(4) cache coherence issue

["Jason Thorpe via gnats" <gnats-admin%NetBSD.org@localhost>]

The following reply was made to PR kern/60144; it has been noted by GNATS.

From: Jason Thorpe <thorpej%me.com@localhost>
To: Tetsuya Isaki <isaki%pastel-flower.jp@localhost>
Cc: gnats-bugs%netbsd.org@localhost,
 kern-bug-people%netbsd.org@localhost,
 netbsd-bugs%netbsd.org@localhost
Subject: Re: kern/60144: virtio(4) cache coherence issue
Date: Thu, 2 Apr 2026 05:42:10 -0700

 > On Apr 2, 2026, at 5:00=E2=80=AFAM, Tetsuya Isaki =
 <isaki%pastel-flower.jp@localhost> wrote:
 >=20
 > At Tue, 31 Mar 2026 06:46:34 -0700,
 > Jason Thorpe wrote:
 >> Please try:
 >>=20
 >>    virt68k/virt68k/bus_dma.c:
 >>=20
 >> $NetBSD: bus_dma.c,v 1.5 2026/03/31 13:45:00 thorpej Exp $
 >=20
 > The spurious interrupt issue still occurs with this bus_dma.c,v 1.5
 > patch.  When I rewrote it as below, the issue didn't seem to occur.
 >=20
 > -       if (ops & BUS_DMASYNC_PREREAD) {
 > +       if (ops & BUS_DMASYNC_POSTREAD) {
 
 If that=E2=80=99s the case, then I=E2=80=99d be concerned that there=E2=80=
 =99s some other issue in the virtio code that could cause a problem on =
 68040 as well, because what it indicates is that, after the cache was =
 invalidated, something accessed the relevant memory (or memory adjacent =
 enough to the relevant memory) that caused a cache line fill to take =
 place, thus putting data that=E2=80=99s about to be stale back into the =
 cache.  The reason this would be problematic on 68040 is that the cache =
 is configured to write-back mode and thus if any of the lines covering =
 the relevant memory were to become dirty, the cache write-back would =
 clobber the data just read into that memory as part of the DMA =
 transaction.
 
 Now, on real hardware there=E2=80=99s a catch: when DMA is taking place, =
 the bus arbitration that the DMA controller engages in to acquire the =
 bus for the DMA operation may, in fact, stall the cache fill, which =
 could make this particular programming error harder to detect.  Does =
 your implementation of 68030 cache emulation model the bus arbitration =
 behavior?
 
 > By the way I've tested it on -11 branch.  (because virt68k-current has
 > another issue.  I'll report once this issue is resolved)
 
 I=E2=80=99m assuming on emulated-68030 only?  In any case, thanks, =
 looking forward to the report.
 
 -- thorpej