Re: kern/60144: virtio(4) cache coherence issue

[Tetsuya Isaki <isaki%pastel-flower.jp@localhost>]

At Mon, 30 Mar 2026 03:47:22 +0000,
Taylor R Campbell wrote:
> > I think that vq_sync_uring_header(sc, vq, BUS_DMASYNC_PREREAD) is
> > necessary to invalidate the cache line before reading fresh
> > vq->vq_used->idx (at line 610) ?
> 
> I believe you have got the usage model of the preread vs postread
> wrong -- it is confusing, because `PREREAD' does not mean `before we
> read from the buffer' but rather `before the device does a DMA read
> operation to initialize the buffer'.
(snip)

Thank you for explanation!
It's confusing...

> If some kind of cache invalidation must happen between the interrupt
> delivery or DMA_STATUS_REG read at (3), and the use of the data in the
> buffer at (5), then the m68k and virt68k bus_dmamap_sync logic might
> be missing something for BUS_DMAMAP_POSTREAD -- it seems to have cases
> only for BUS_DMAMAP_PREWRITE and BUS_DMAMAP_PREREAD:
> 
> https://nxr.NetBSD.org/xref/src/sys/arch/m68k/m68k/bus_dma.c?r=1.41#491
> https://nxr.NetBSD.org/xref/src/sys/arch/virt68k/virt68k/bus_dma.c?r=1.4#476
> 
> Perhaps m68k needs new POSTREAD logic to be written, or perhaps there
> was a mistake and the PREREAD logic should have been for POSTREAD?

Hmm, that's it... Thanks!

sys/arch/virt68k/virt68k/bus_dma.c:
  429 void
  430 _bus_dmamap_sync_030(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
  431     bus_size_t len, int ops)
  432 {
  433
  434     /* Nothing yet */
  435 }

I try to implement (and test) it.
Or would someone take this?
---
Tetsuya Isaki <isaki%pastel-flower.jp@localhost / isaki%NetBSD.org@localhost>