Re: kern/60144: virtio(4) cache coherence issue

[Tetsuya Isaki <isaki%pastel-flower.jp@localhost>]

At Mon, 30 Mar 2026 16:45:02 +0000 (UTC),
Robert Elz via gnats wrote:
>    | This actually brings up an interesting philosophical question:
>    | What does DMA coherency mean in the context of virtio?
>  
>  Well, as you suggest, but didn't explicitly say, caching in a virtual
>  device can't logically be to make anything run faster, so the obvious
>  interpretation would be that it is intended to assist in finding caching
>  bugs.

Mostly yes.
In my emulator, I tend to focus on accuracy (though performance is
also important).
If asked why you are implementing a cache (even though it could not
contribute to performance), my answer is "because it's there." :)

But seriously, though it's off topic,
speaking of 68030, it is VA cache.  When a cache hit occurs,
it can skip not only memory access but also both ATC lookup and
table search.  So, my cache implementation also contributed to
performance well on my 68030 emulation.
---
Tetsuya Isaki <isaki%pastel-flower.jp@localhost / isaki%NetBSD.org@localhost>