PR/55139 CVS commit: src/sys/arch/mips/include

["Izumi Tsutsui" <tsutsui%netbsd.org@localhost>]

The following reply was made to PR port-mips/55139; it has been noted by GNATS.

From: "Izumi Tsutsui" <tsutsui%netbsd.org@localhost>
To: gnats-bugs%gnats.NetBSD.org@localhost
Cc: 
Subject: PR/55139 CVS commit: src/sys/arch/mips/include
Date: Fri, 5 Dec 2025 18:33:28 +0000

 Module Name:	src
 Committed By:	tsutsui
 Date:		Fri Dec  5 18:33:28 UTC 2025
 
 Modified Files:
 	src/sys/arch/mips/include: cache_r5k.h
 
 Log Message:
 mips: Fix R5000SC cache page macro typo that broke boot.
 
 A change in rev 1.5 to mips_r5k_round_page() and mips_r5k_trunc_page()
 in cache_r5k.h (for PR/55139) had a fatal typo in the mask, so the
 R5000SC cache flush code ended up operating on unintended addresses
 and at least R5000SC Indy would no longer boot.
 (not sure how my Qube 2700 worked at that time..)
 
 Fix the macros to use the intended mask so that the secondary cache
 flushes are done on the correct range again.
 
 Sorry for the long breakage.
 
 Analyzed and reported by Adrian Chadd on port-mips@.
  https://mail-index.netbsd.org/port-mips/2025/12/thread1.html#001536
 
 Should be pulled up to netbsd-9, netbsd-10, and netbsd-11.
 
 
 To generate a diff of this commit:
 cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/include/cache_r5k.h
 
 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.