Re: port-mips/57680: printf("%.1f") shows wrong results on R3000mipseb

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

The following reply was made to PR port-mips/57680; it has been noted by GNATS.

From: Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>
To: campbell%mumble.net@localhost
Cc: riastradh%NetBSD.org@localhost, gnats-bugs%netbsd.org@localhost, tsutsui%ceres.dti.ne.jp@localhost
Subject: Re: port-mips/57680: printf("%.1f") shows wrong results on R3000mipseb
Date: Thu, 16 Nov 2023 23:40:07 +0900

 I wrote:
 > I'll check binutils diff between netbsd-7 and 8.
 
 Okay, I think I've got it.
 
 Index: gas/config/tc-mips.c
 ===================================================================
 RCS file: /cvsroot/src/external/gpl3/binutils/dist/gas/config/tc-mips.c,v
 retrieving revision 1.21
 diff -u -p -d -U 20 -r1.21 tc-mips.c
 --- gas/config/tc-mips.c	7 Nov 2018 01:13:53 -0000	1.21
 +++ gas/config/tc-mips.c	16 Nov 2023 14:18:10 -0000
 @@ -6423,42 +6423,42 @@ insns_between (const struct mips_cl_insn
    if (!HAVE_CODE_COMPRESSION)
      {
        /* Check for GPR or coprocessor load delays.  All such delays
  	 are on the RT register.  */
        /* Itbl support may require additional care here.  */
        if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
  	  || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
  	{
  	  if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
  	    return 1;
  	}
  
        /* Check for generic coprocessor hazards.
  
  	 This case is not handled very well.  There is no special
  	 knowledge of CP0 handling, and the coprocessors other than
  	 the floating point unit are not distinguished at all.  */
        /* Itbl support may require additional care here. FIXME!
  	 Need to modify this to include knowledge about
  	 user specified delays!  */
 -      else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
 -	       || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
 +      if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
 +	  || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
  	{
  	  /* Handle cases where INSN1 writes to a known general coprocessor
  	     register.  There must be a one instruction delay before INSN2
  	     if INSN2 reads that register, otherwise no delay is needed.  */
  	  mask = fpr_write_mask (insn1);
  	  if (mask != 0)
  	    {
  	      if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
  		return 1;
  	    }
  	  else
  	    {
  	      /* Read-after-write dependencies on the control registers
  		 require a two-instruction gap.  */
  	      if ((pinfo1 & INSN_WRITE_COND_CODE)
  		  && (pinfo2 & INSN_READ_COND_CODE))
  		return 2;
  
  	      /* We don't know exactly what INSN1 does.  If INSN2 is
  		 also a coprocessor instruction, assume there must be
 
 ---
 
 The pinfo field has been changed between binutils 2.23.2 and 2.27.
 After the change, INSN_LOAD_MEMORY can be defined both GPR and FPR.
 Actually on binutils 2.27 pinfo of lwc1 is 01020811, i.e.
 (FP_S|INSN_COPROC_MEMORY_DELAY|INSN_LOAD_MEMORY|INSN_READ_3|INSN_WRITE_1),
 but tc-mips.c still uses "else if" after an INSN_LOAD_MEMORY check
 against GPR as above.
 
 ---
 Izumi Tsutsui