port-hppa/56865: hppa: t_ptrace_core_wait test doesn't know it must advance PC after breakpoint

[tgl%sss.pgh.pa.us@localhost]

>Number:         56865
>Category:       port-hppa
>Synopsis:       hppa: t_ptrace_core_wait test doesn't know it must advance PC after breakpoint
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    port-hppa-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Tue Jun 07 01:25:00 +0000 2022
>Originator:     Tom Lane
>Release:        HEAD/202206030100Z
>Organization:
PostgreSQL Global Development Group
>Environment:
NetBSD sss2.sss.pgh.pa.us 9.99.97 NetBSD 9.99.97 (SD2) #0: Fri Jun  3 12:30:06 EDT 2022  tgl%nuc1.sss.pgh.pa.us@localhost:/home/tgl/netbsd-H-202206030100Z/obj.hppa/sys/arch/hppa/compile/SD2 hppa
>Description:
The lib/libc/sys/t_ptrace_wait:core_dump_procinfo test case consistently fails on HPPA.  This turns out to be because the test doesn't know that on HPPA a breakpoint trap reports the address of the break instruction, so PC has to be advanced to continue afterwards.
>How-To-Repeat:
$ cd /usr/tests
$ atf-run lib/libc/sys/t_ptrace_wait

Note core_dump_procinfo failure.

(This is not the only failure in that test program, but I'm filing it separately since it's a distinct problem.)

>Fix:
Index: tests/lib/libc/sys/t_ptrace_core_wait.h
===================================================================
RCS file: /cvsroot/src/tests/lib/libc/sys/t_ptrace_core_wait.h,v
retrieving revision 1.5
diff -u -r1.5 t_ptrace_core_wait.h
--- tests/lib/libc/sys/t_ptrace_core_wait.h     26 Mar 2022 16:22:50 -0000      1.5
+++ tests/lib/libc/sys/t_ptrace_core_wait.h     6 Jun 2022 18:09:37 -0000
@@ -209,7 +209,7 @@
            "without signal to be sent\n");
 
 #if defined(__aarch64__) || defined(__arm__) || defined(__powerpc__) || \
-    defined(__sh3__) || defined(sparc)
+    defined(__sh3__) || defined(sparc) || defined(__hppa__)
        /*
         * For these archs, program counter is not automatically incremented
         * by a trap instruction. We cannot increment PC in the trap handler,