Re: port-mips/55139: Misunderstanding on R5000 L2 cachePage_Invalidate(S) op size

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

The following reply was made to PR port-mips/55139; it has been noted by GNATS.

From: Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>
To: nick.hudson%gmx.co.uk@localhost
Cc: gnats-bugs%netbsd.org@localhost, tsutsui%ceres.dti.ne.jp@localhost
Subject: Re: port-mips/55139: Misunderstanding on R5000 L2 cachePage_Invalidate(S)
	 op size
Date: Sat, 4 Apr 2020 22:21:00 +0900

 > why isn't this correct? I didn't follow your logic
 
 There are two points:
 
 1) trunc/round macros were changed from "(128 * 32)" to "PAGE_SIZE", but
    a corresponding increment count in iteration was left as "(128 * 32)".
    (I'm not sure if it was intentional or not)
 
 2) R5000 Page_Invalidate_S op flushes fixed 4096 bytes (128 lines),
    but "PAGE_SIZE" on MIPS3 is no longer 4096 (== 128 * 32) by default:
 
  https://nxr.netbsd.org/xref/src/sys/arch/mips/include/mips_param.h?r=1.38#87
 ---
 #ifdef ENABLE_MIPS_16KB_PAGE
 #define	PGSHIFT		14		/* LOG2(NBPG) */
 #elif defined(ENABLE_MIPS_8KB_PAGE) \
     || (!defined(ENABLE_MIPS_4KB_PAGE) && __mips >= 3)
 #define	PGSHIFT		13		/* LOG2(NBPG) */
 #else
 #define	PGSHIFT		12		/* LOG2(NBPG) */
 #endif
 ---
 
 ---
 Izumi Tsustui