Re: port-mips/55139: Misunderstanding on R5000 L2 cache Page_Invalidate(S) op size

[Nick Hudson <nick.hudson%gmx.co.uk@localhost>]

On 03/04/2020 19:05, Izumi Tsutsui wrote:
> > Number:         55139
[snip]

> but "(128 * 32)" (i.e. 4096) is used in the flush address iteration:
> > > 	for (; va < eva; va += (128 * 32)) {
> > > 		cache_op_r4k_line(va, CACHEOP_R4K_HIT_WB_INV|CACHE_R4K_SD);
> > > 	}

[snip]

why isn't this correct? I didn't follow your logic


> R5000 L2 cacheline size is 32, so the the original implementation
> "(128 * 32)" shall be a correct for R5000 Page Invalidate (S) op,
> and PAGE_SIZE is not correct. Extra truncation/roundup aginst flush
> regions would be harmless except small performance penalty, though.

sys/arch/mips/mips/cache_r5k.c:1.17 just did the extra-truncation/roundup.

I'm obviously missing something here...

Nick