port-mips/55138: R5000 suspicious picache settings

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

>Number:         55138
>Category:       port-mips
>Synopsis:       R5000 suspicious picache settings
>Confidential:   no
>Severity:       non-critical
>Priority:       medium
>Responsible:    port-mips-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Fri Apr 03 17:15:00 +0000 2020
>Originator:     Izumi Tsutsui
>Release:        NetBSD 9.0
>Organization:
>Environment:
System: NetBSD 9.0 
Architecture: mips
Machine: R5000 mips
>Description:
sys/arch/mips/mips/cache.c has the following code:
---
	case MIPS_R4600:
#ifdef ENABLE_MIPS_R4700
	case MIPS_R4700:
#endif
#ifndef ENABLE_MIPS_R3NKK
	case MIPS_R5000:
#endif
	case MIPS_RM5200:
primary_cache_is_2way:

 [...]

		switch (mci->mci_picache_line_size) {
		case 32:
			/* used internally by mipsNN_picache_sync_range */
			mco->mco_intern_icache_sync_range =
			    cache_r4k_icache_hit_inv_16;

			/* used internally by mipsNN_picache_sync_range_index */
			mco->mco_intern_icache_sync_range_index =
			    cache_r4k_icache_index_inv_16;
			break;

		default:
			panic("r5k picache line size %u",
			    mci->mci_picache_line_size);
		}
---

I.e. _16 cacheline functions (cache_r4k_icache_hit_inv_16
and cache_r4k_icache_index_inv_16) are specified in
mci_picache_line_size == 32 case for R5000.

In R4000 case actual cacheline size ops are specified.
---
		switch (mci->mci_picache_line_size) {
		case 16:
			mco->mco_icache_sync_range =
			    cache_r4k_icache_hit_inv_16;
			mco->mco_icache_sync_range_index =
			    cache_r4k_icache_index_inv_16;
			break;

		case 32:
			mco->mco_icache_sync_range =
			    cache_r4k_icache_hit_inv_32;
			mco->mco_icache_sync_range_index =
			    cache_r4k_icache_index_inv_32;
			break;
---

>How-To-Repeat:
Code inspection.

>Fix:
No idea if it's intentional design or bad copy and paste.