Re: kern/55115 (siisata(4) broken after enabling MSI support)

To: jdolecek%netbsd.org@localhost, gnats-admin%netbsd.org@localhost, netbsd-bugs%netbsd.org@localhost, jdbaker%consolidated.net@localhost
Subject: Re: kern/55115 (siisata(4) broken after enabling MSI support)
From: "John D. Baker" <jdbaker%consolidated.net@localhost>
Date: Sat, 28 Mar 2020 12:10:02 +0000 (UTC)
The following reply was made to PR kern/55115; it has been noted by GNATS.

From: "John D. Baker" <jdbaker%consolidated.net@localhost>
To: gnats-bugs%netbsd.org@localhost
Cc: 
Subject: Re: kern/55115 (siisata(4) broken after enabling MSI support)
Date: Sat, 28 Mar 2020 07:07:45 -0500 (CDT)

 On Sat, 28 Mar 2020, jdolecek%NetBSD.org@localhost wrote:
 
 > I committed the MSI change, I'll look into this. Can you please include
 > the pcictl dump for the device? It may be there is more than one MSI vector,
 > and the device triggers different MSI interrupts according to channel.
 
 When it fails (MSI enabled):
 
 PCI configuration registers:
   Common header:
     0x00: 0x31241095 0x02b8009f 0x01040002 0x00004010
 
     Vendor Name: CMD Technology (0x1095)
     Device Name: SiI3124 SATALink (0x3124)
     Command register: 0x009f
       I/O space accesses: on
       Memory space accesses: on
       Bus mastering: on
       Special cycles: on
       MWI transactions: on
       Palette snooping: off
       Parity error checking: off
       Address/data stepping: on
       System error (SERR): off
       Fast back-to-back transactions: off
       Interrupt disable: off
     Status register: 0x02b8
       Immediate Readiness: off
       Interrupt status: active
       Capability List support: on
       66 MHz capable: on
       User Definable Features (UDF) support: off
       Fast back-to-back capable: on
       Data parity error detected: off
       DEVSEL timing: medium (0x1)
       Slave signaled Target Abort: off
       Master received Target Abort: off
       Master received Master Abort: off
       Asserted System Error (SERR): off
       Parity error detected: off
     Class Name: mass storage (0x01)
     Subclass Name: RAID (0x04)
     Interface: 0x00
     Revision ID: 0x02
     BIST: 0x00
     Header Type: 0x00 (0x00)
     Latency Timer: 0x40
     Cache Line Size: 64bytes (0x10)
 
   Type 0 ("normal" device) header:
     0x10: 0xe8008004 0x00000000 0xe8000004 0x00000000
     0x20: 0x00001001 0x00000000 0x00000000 0x71241095
     0x30: 0xfff80000 0x00000064 0x00000000 0x00000109
 
     Base address register at 0x10
       type: 64-bit nonprefetchable memory
       base: 0x00000000e8008000
     Base address register at 0x18
       type: 64-bit nonprefetchable memory
       base: 0x00000000e8000000
     Base address register at 0x20
       type: I/O
       base: 0x00001000
     Base address register at 0x24
       not implemented
     Cardbus CIS Pointer: 0x00000000
     Subsystem vendor ID: 0x1095
     Subsystem ID: 0x7124
     Expansion ROM Base Address Register: 0xfff80000
       base: 0xfff80000
       Expansion ROM Enable: off
       Validation Status: Validation not supported
       Validation Details: 0x0
     Capability list pointer: 0x64
     Reserved @ 0x38: 0x00000000
     Maximum Latency: 0x00
     Minimum Grant: 0x00
     Interrupt pin: 0x01 (pin A)
     Interrupt line: 0x09
 
   Capability register at 0x64
     type: 0x01 (Power Management)
   Capability register at 0x40
     type: 0x07 (PCI-X)
   Capability register at 0x54
     type: 0x05 (MSI)
 
   PCI Power Management Capabilities Register
     Capabilities register: 0x0622
       Version: 1.1
       PME# clock: off
       Device specific initialization: on
       3.3V auxiliary current: self-powered
       D1 power management state support: on
       D2 power management state support: on
       PME# support D0: off
       PME# support D1: off
       PME# support D2: off
       PME# support D3 hot: off
       PME# support D3 cold: off
     Control/status register: 0x00002000
       Power state: D0
       PCI Express reserved: off
       No soft reset: off
       PME# assertion: disabled
       Data Select: 0
       Data Scale: 1
       PME# status: off
     Bridge Support Extensions register: 0x00
       B2/B3 support: off
       Bus Power/Clock Control Enable: off
     Data register: 0x00
 
   PCI Message Signaled Interrupt
     Message Control register: 0x0081
       MSI Enabled: on
       Multiple Message Capable: no (1 vector)
       Multiple Message Enabled: off (1 vector)
       64 Bit Address Capable: on
       Per-Vector Masking Capable: off
       Extended Message Data Capable: off
       Extended Message Data Enable: off
     Message Address (lower) register: 0xfee00000
     Message Address (upper) register: 0x00000000
     Message Data register: 0x0063
 
   PCI-X Non-bridge Capabilities Register
     Command register: 0x0052
       Data Parity Error Recovery: off
       Enable Relaxed Ordering: on
       Maximum Burst Read Count: 512
       Maximum Split Transactions: 12
     Status register: 0x12c3fff8
       Function: 0
       Device: 31
       Bus: 255
       64bit device: on
       133MHz capable: on
       Split completion discarded: off
       Unexpected split completion: off
       Device Complexity: simple device
       Designed max memory read byte count: 2048
       Designed max outstanding split transaction: 12
       MAX cumulative Read Size: 128
       Received split completion error: off
       266MHz capable: off
       533MHz capable: off
 
   Device-dependent header:
     0x40: 0x00525407 0x12c3fff8 0x00000000 0x00000000
     0x50: 0x00000000 0x00810005 0xfee00000 0x00000000
     0x60: 0x00000063 0x06224001 0x19002000 0x00000000
     0x70: 0x00000000 0x00000000 0x00000000 0x00000000
     0x80: 0x00000000 0x00000000 0x00000000 0x00000000
     0x90: 0x00000000 0x00000000 0x00000000 0x00000000
     0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
 
 
 When it works (MSI disabled):
 
 PCI configuration registers:
   Common header:
     0x00: 0x31241095 0x02b0009f 0x01040002 0x00004010
 
     Vendor Name: CMD Technology (0x1095)
     Device Name: SiI3124 SATALink (0x3124)
     Command register: 0x009f
       I/O space accesses: on
       Memory space accesses: on
       Bus mastering: on
       Special cycles: on
       MWI transactions: on
       Palette snooping: off
       Parity error checking: off
       Address/data stepping: on
       System error (SERR): off
       Fast back-to-back transactions: off
       Interrupt disable: off
     Status register: 0x02b0
       Immediate Readiness: off
       Interrupt status: inactive
       Capability List support: on
       66 MHz capable: on
       User Definable Features (UDF) support: off
       Fast back-to-back capable: on
       Data parity error detected: off
       DEVSEL timing: medium (0x1)
       Slave signaled Target Abort: off
       Master received Target Abort: off
       Master received Master Abort: off
       Asserted System Error (SERR): off
       Parity error detected: off
     Class Name: mass storage (0x01)
     Subclass Name: RAID (0x04)
     Interface: 0x00
     Revision ID: 0x02
     BIST: 0x00
     Header Type: 0x00 (0x00)
     Latency Timer: 0x40
     Cache Line Size: 64bytes (0x10)
 
   Type 0 ("normal" device) header:
     0x10: 0xe8008004 0x00000000 0xe8000004 0x00000000
     0x20: 0x00001001 0x00000000 0x00000000 0x71241095
     0x30: 0xfff80000 0x00000064 0x00000000 0x00000109
 
     Base address register at 0x10
       type: 64-bit nonprefetchable memory
       base: 0x00000000e8008000
     Base address register at 0x18
       type: 64-bit nonprefetchable memory
       base: 0x00000000e8000000
     Base address register at 0x20
       type: I/O
       base: 0x00001000
     Base address register at 0x24
       not implemented
     Cardbus CIS Pointer: 0x00000000
     Subsystem vendor ID: 0x1095
     Subsystem ID: 0x7124
     Expansion ROM Base Address Register: 0xfff80000
       base: 0xfff80000
       Expansion ROM Enable: off
       Validation Status: Validation not supported
       Validation Details: 0x0
     Capability list pointer: 0x64
     Reserved @ 0x38: 0x00000000
     Maximum Latency: 0x00
     Minimum Grant: 0x00
     Interrupt pin: 0x01 (pin A)
     Interrupt line: 0x09
 
   Capability register at 0x64
     type: 0x01 (Power Management)
   Capability register at 0x40
     type: 0x07 (PCI-X)
   Capability register at 0x54
     type: 0x05 (MSI)
 
   PCI Power Management Capabilities Register
     Capabilities register: 0x0622
       Version: 1.1
       PME# clock: off
       Device specific initialization: on
       3.3V auxiliary current: self-powered
       D1 power management state support: on
       D2 power management state support: on
       PME# support D0: off
       PME# support D1: off
       PME# support D2: off
       PME# support D3 hot: off
       PME# support D3 cold: off
     Control/status register: 0x00002000
       Power state: D0
       PCI Express reserved: off
       No soft reset: off
       PME# assertion: disabled
       Data Select: 0
       Data Scale: 1
       PME# status: off
     Bridge Support Extensions register: 0x00
       B2/B3 support: off
       Bus Power/Clock Control Enable: off
     Data register: 0x00
 
   PCI Message Signaled Interrupt
     Message Control register: 0x0080
       MSI Enabled: off
       Multiple Message Capable: no (1 vector)
       Multiple Message Enabled: off (1 vector)
       64 Bit Address Capable: on
       Per-Vector Masking Capable: off
       Extended Message Data Capable: off
       Extended Message Data Enable: off
     Message Address (lower) register: 0x00000000
     Message Address (upper) register: 0x00000000
     Message Data register: 0x0000
 
   PCI-X Non-bridge Capabilities Register
     Command register: 0x0052
       Data Parity Error Recovery: off
       Enable Relaxed Ordering: on
       Maximum Burst Read Count: 512
       Maximum Split Transactions: 12
     Status register: 0x12c3fff8
       Function: 0
       Device: 31
       Bus: 255
       64bit device: on
       133MHz capable: on
       Split completion discarded: off
       Unexpected split completion: off
       Device Complexity: simple device
       Designed max memory read byte count: 2048
       Designed max outstanding split transaction: 12
       MAX cumulative Read Size: 128
       Received split completion error: off
       266MHz capable: off
       533MHz capable: off
 
   Device-dependent header:
     0x40: 0x00525407 0x12c3fff8 0x00000000 0x00000000
     0x50: 0x00000000 0x00800005 0x00000000 0x00000000
     0x60: 0x00000000 0x06224001 0x19002000 0x00000000
     0x70: 0x00000000 0x00000000 0x00000000 0x00000000
     0x80: 0x00000000 0x00000000 0x00000000 0x00000000
     0x90: 0x00000000 0x00000000 0x00000000 0x00000000
     0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
     0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
 
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