port-mips/51315: (todo) MIPS1 DIAGNOSTIC assert failed: pcb2->pcb_context.val[_L_SR] & MIPS_SR_INT_IE

[coypu%sdf.org@localhost]

>Number:         51315
>Category:       port-mips
>Synopsis:       (todo) MIPS1 DIAGNOSTIC assert failed: pcb2->pcb_context.val[_L_SR] & MIPS_SR_INT_IE
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    port-mips-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Tue Jul 05 22:40:00 +0000 2016
>Originator:     coypu
>Release:        NetBSD-7.99.33
>Organization:
>Environment:
NetBSD  7.99.33 NetBSD 7.99.33 (GENERIC-DEBUG) #25: Tue Jul  5 22:50:56 IDT 2016  fly%net.Home@localhost:/obj/pmax/sys/arch/pmax/compile/GENERIC-DEBUG pmax
>Description:
Booting a DIAGNOSTIC kernel on any MIPS1 machine (or gxemul -e 3max, booting a full install, not installer) panics:

pid 1(init): ABI set to O32 (e_flags=0x1007)
panic: kernel diagnostic assertion "pcb2->pcb_context.val[_L_SR] & MIPS_SR_INT_IE" failed: file "/usr/cvs-src/src/sys/arch/mips/mips/vm_machdep.c", line 150 14.1 0x80034
cpu0: Begin traceback...
pid -1020740368 not found
cpu0: End traceback...
0xc328bd00: cpu_reboot+38 (104,0,0,804e2ca0) ra 80314c5c sz 24
0xc328bd18: vpanic+1b0 (104,0,0,804e2ca0) ra 804139c0 sz 48
0xc328bd48: kern_assert+40 (104,8043adbc,8043faec,8043fb1c) ra 800527e8 sz 32
0xc328bd68: cpu_lwp_fork+218 (104,8043adbc,8043faec,8043fb1c) ra 802837a0 sz 64
0xc328bda8: uvm_lwp_fork+28 (104,8043adbc,8043faec,8043fb1c) ra 802c78c4 sz 32
0xc328bdc8: lwp_create+2d8 (104,8043adbc,8043faec,8043fb1c) ra 802bef4c sz 64
0xc328be08: fork1+44c (104,8043adbc,14,8043fb1c) ra 802bf69c sz 144
0xc328be98: sys_fork+2c (104,8043adbc,c328bf68,8043fb1c) ra 8004ec80 sz 48
0xc328bec8: syscall+260 (104,8043adbc,c328bf68,8043fb1c) ra 80041598 sz 128
0xc328bf48: mips1_systemcall+ec (104,8043adbc,c328bf68,8043fb1c) ra 7de726e0 sz 0

This is because MIPS1 interrupt enable bit is different.
Currently we use just MIPS_SR_INT_IE = 0x1, and initialize lwp0 to have this value in pcb_context.val[_L_SR]. It is later copied to all processes.

A valid assert test for MIPS1 would be:
(STATUS & 0xf) == 0xc

And the initial value (for lwp0) should be set differently, as well.

interrupt changes by hardware (among them, the 'rfe' call in kern_return) change the STATUS according to what MIPS1 should have for enabling interrupts, causing a conflict where the STATUS seems to have interrupts disabled when they are in fact, enabled.

The fixes will not be committed as this bug does not seem to cause an actual problem with real hardware, aside from the DIAGNOSTIC panic.
A fix will cause the second MIPS apocalypse^Wpatch to have merge conflicts, unnecessarily.

A temporary workaround is to comment out the assert.
>How-To-Repeat:

>Fix: