Re: kern/49076: USB 3.0 devices are not attached to xhci hubs

[Ryo ONODERA <ryo_on%yk.rim.or.jp@localhost>]

The following reply was made to PR kern/49076; it has been noted by GNATS.

From: Ryo ONODERA <ryo_on%yk.rim.or.jp@localhost>
To: gnats-bugs%NetBSD.org@localhost
Cc: 
Subject: Re: kern/49076: USB 3.0 devices are not attached to xhci hubs
Date: Sat, 16 Aug 2014 22:19:34 +0900 (JST)

 Hi,
 
 The following patch enables xhci ports on
 "vendor 0x8086 product 0x8c31" (Lenovo ThinkStation E32's)
 and chip on Apple MacBook Air early 2014 11-inch.
 
 On the MacBook Air, cv_timedwait in xhci_do_command (it is invoked from
 xhci_enable_slot) returns EWOULDBLOCK, and I cannot get working ports.
 So no device is unusable.
 
 On ThinkStation E32, it works almost fine with my patch.
 And my Fresco Logic xhci (vendor 0x1b73 product 0x1100) also works
 with my patch.
 
 This patch is inspired from FreeBSD and Linux code.
 
 Index: sys/dev/pci/xhci_pci.c
 ===================================================================
 RCS file: /cvsroot/src/sys/dev/pci/xhci_pci.c,v
 retrieving revision 1.3
 diff -u -r1.3 xhci_pci.c
 --- sys/dev/pci/xhci_pci.c     29 Mar 2014 19:28:25 -0000      1.3
 +++ sys/dev/pci/xhci_pci.c     16 Aug 2014 12:57:08 -0000
 @@ -86,6 +86,7 @@
        //const char *vendor;
        uint32_t hccparams;
        char intrbuf[PCI_INTRSTR_LEN];
 +      pcireg_t ports_available;
  
        sc->sc_dev = self;
        sc->sc_bus.hci_private = sc;
 @@ -165,6 +166,18 @@
                    "vendor 0x%04x", PCI_VENDOR(pa->pa_id));
  #endif
  
 +/*
 + * Intel's xHCI host controller in Panther Point chipset requires
 + * Intel specific register handling to enable ports.
 + */
 +      ports_available = pci_conf_read(pc, tag, PCI_XHCI_INTEL_USB3PRM);
 +      pci_conf_write(pc, tag, PCI_XHCI_INTEL_USB3_PSSEN, ports_available);
 +      ports_available = pci_conf_read(pc, tag, PCI_XHCI_INTEL_USB3_PSSEN);
 +
 +      ports_available = pci_conf_read(pc, tag, PCI_XHCI_INTEL_USB2PRM);
 +      pci_conf_write(pc, tag, PCI_XHCI_INTEL_XUSB2PR, ports_available);
 +      ports_available = pci_conf_read(pc, tag, PCI_XHCI_INTEL_XUSB2PR);
 +
        err = xhci_init(sc);
        if (err) {
                aprint_error_dev(self, "init failed, error=%d\n", err);
 Index: sys/dev/usb/xhcireg.h
 ===================================================================
 RCS file: /cvsroot/src/sys/dev/usb/xhcireg.h,v
 retrieving revision 1.1
 diff -u -r1.1 xhcireg.h
 --- sys/dev/usb/xhcireg.h      14 Sep 2013 00:40:31 -0000      1.1
 +++ sys/dev/usb/xhcireg.h      16 Aug 2014 12:57:08 -0000
 @@ -34,10 +34,15 @@
  #define       PCI_INTERFACE_XHCI      0x30
  
  #define       PCI_USBREV              0x60    /* RO USB protocol revision */
 -#define        PCI_USBREV_MASK        0xFF
 -#define        PCI_USBREV_3_0         0x30    /* USB 3.0 */
 +#define       PCI_USBREV_MASK         0xFF
 +#define       PCI_USBREV_3_0          0x30    /* USB 3.0 */
  #define       PCI_XHCI_FLADJ          0x61    /* RW frame length adjust */
  
 +#define       PCI_XHCI_INTEL_XUSB2PR  0xD0    /* Intel USB2 Port Routing */
 +#define       PCI_XHCI_INTEL_USB2PRM  0xD4    /* Intel USB2 Port Routing Mask 
*/
 +#define       PCI_XHCI_INTEL_USB3_PSSEN 0xD8  /* Intel USB3 Port SuperSpeed 
Enable */
 +#define       PCI_XHCI_INTEL_USB3PRM  0xDC    /* Intel USB3 Port Routing Mask 
*/
 +
  /* XHCI capability registers */
  #define XHCI_CAPLENGTH                0x00    /* RO capability */
  #define       XHCI_CAP_CAPLENGTH(x)   ((x) & 0xFF)
 
 --
 Ryo ONODERA // ryo_on%yk.rim.or.jp@localhost
 PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB  FD1B F404 27FA C7D1 15F3