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Re: port-alpha/48148: NetBSD/alpha fails to install on AlphaStaion DS15
> >Synopsis: NetBSD/alpha fails to install on AlphaStaion DS15
I've discussed with the submitter and reviewed his patch.
I'd note results in the PR for reference (since I'm not an alpha guy).
> --- alpha.orig/alpha/cpuconf.c 2012-02-06 02:14:10.000000000 +0000
> +++ alpha/alpha/cpuconf.c 2013-08-22 22:16:00.000000000 +0000
> @@ -233,6 +233,7 @@
> cpu_notsupp(ST_DEC_EV56_PBP, "EV56 Passive Backplane Board"),
> cpu_notsupp(ST_DEC_ALPHAVME_320, "AlphaVME 320"),
> cpu_init(ST_DEC_6600, dec_6600_init, "DEC_6600"),
> + cpu_init(ST_DEC_TITAN, dec_6600_init, "DEC_6600"),
> cpu_init(ST_API_NAUTILUS, api_up1000_init, "API_UP1000"),
I wonder if it's better to change strings "DEC_TITAN"
but it's easier to sync with the original OpenBSD's code.
> --- alpha.orig/include/rpb.h 2012-02-06 02:14:13.000000000 +0000
> +++ alpha/include/rpb.h 2013-08-22 22:21:48.000000000 +0000
> @@ -452,7 +452,7 @@
> u_long mddt_p_bitaddr; /* 20: bitmap phys addr */
> int64_t mddt_bit_cksum; /* 28: bitmap checksum */
>
> -#define MDDT_NONVOLATILE 0x10 /* cluster is
> non-volatile */
> +#define MDDT_NONVOLATILE 0x02 /* cluster is non-volatile */
> #define MDDT_PALCODE 0x01 /* console and PAL only
> */
This change is not necessary for DS15 support and
taken from a different change in OpenBSD:
http://www.openbsd.org/cgi-bin/cvsweb/src/sys/arch/alpha/include/rpb.h#rev1.11
It looks correct but it should be in a separate commit.
> --- alpha.orig/pci/tsc.c 2011-05-17 17:34:47.000000000 +0000
> +++ alpha/pci/tsc.c 2013-08-22 22:46:14.000000000 +0000
:
> + switch (cputype) {
> + case ST_DEC_6600:
> + case ST_DEC_TITAN:
> + return strcmp(ma->ma_name, tsc_cd.cd_name) == 0 && !tscfound;
> + default:
> + return 0;
> + }
> +
> +
> }
>
> static void
> @@ -104,15 +110,17 @@
> uint64_t csc, aar;
> struct tsp_attach_args tsp;
> struct mainbus_attach_args *ma = aux;
> + int titan = cputype == ST_DEC_TITAN;
> +
>
Extra lines should not be added.
> @@ -123,20 +131,29 @@
> }
> printf(", Dchip 0 rev %d\n", (int)LDQP(TS_D_DREV) & 0xf);
>
> - memset(&tsp, 0, sizeof tsp);
I'd like to leave this memset() for sanity.
(though all members are initialized later)
> tsp.tsp_name = "tsp";
> - config_found(self, &tsp, NULL);
> + tsp.tsp_slot = 0;
> +
> + config_found(self, &tsp, tscprint);
> + if (titan) {
> + tsp.tsp_slot += 2;
> + config_found(self, &tsp, tscprint);
> + }
>
> - if(LDQP(TS_C_CSC) & CSC_P1P) {
> - ++tsp.tsp_slot;
> + if (csc & CSC_P1P) {
Tab vs space.
> + tsp.tsp_slot = 1;
> + config_found(self, &tsp, tscprint);
> + if (titan) {
> + tsp.tsp_slot += 2;
> config_found(self, &tsp, tscprint);
> }
> + }
Bad indent.
> }
>
> static int
> tscprint(void *aux, const char *p)
> {
> - register struct tsp_attach_args *tsp = aux;
> + struct tsp_attach_args *tsp = aux;
Removing register declarations should be done in a separate commit.
> @@ -193,12 +215,24 @@
> /* n: Pchip number */
> {
> struct tsp_config *pcp;
> + int titan = cputype == ST_DEC_TITAN;
Probably bool is better than int, but for now we'll sync with OpenBSD.
> - KASSERT((n | 1) == 1);
> + KASSERT(n >= 0 && n < nitems(tsp_configuration));
nitems() is OpenBSD specific so it should be __arraycount() on NetBSD.
(note submitter said he tried only kernels without DIAGNOSTIC)
> --- alpha.orig/pci/tsreg.h 2012-02-06 02:14:15.000000000 +0000
> +++ alpha/pci/tsreg.h 2013-08-22 22:56:40.000000000 +0000
I'll remove extra lines to clarify diff.
As a result of review, I'll commit the following patch to head:
---
Index: alpha/cpuconf.c
===================================================================
RCS file: /cvsroot/src/sys/arch/alpha/alpha/cpuconf.c,v
retrieving revision 1.35
diff -u -p -r1.35 cpuconf.c
--- alpha/cpuconf.c 6 Feb 2012 02:14:10 -0000 1.35
+++ alpha/cpuconf.c 16 Sep 2013 15:05:42 -0000
@@ -233,6 +233,7 @@ static const struct cpuinit cpuinit[] =
cpu_notsupp(ST_DEC_EV56_PBP, "EV56 Passive Backplane Board"),
cpu_notsupp(ST_DEC_ALPHAVME_320, "AlphaVME 320"),
cpu_init(ST_DEC_6600, dec_6600_init, "DEC_6600"),
+ cpu_init(ST_DEC_TITAN, dec_6600_init, "DEC_6600"),
cpu_init(ST_API_NAUTILUS, api_up1000_init, "API_UP1000"),
};
static const int ncpuinit = (sizeof(cpuinit) / sizeof(cpuinit[0]));
Index: pci/tsc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/alpha/pci/tsc.c,v
retrieving revision 1.19
diff -u -p -r1.19 tsc.c
--- pci/tsc.c 17 May 2011 17:34:47 -0000 1.19
+++ pci/tsc.c 16 Sep 2013 15:05:42 -0000
@@ -66,7 +66,7 @@ CFATTACH_DECL_NEW(tsc, 0, tscmatch, tsca
extern struct cfdriver tsc_cd;
-struct tsp_config tsp_configuration[2];
+struct tsp_config tsp_configuration[4];
static int tscprint(void *, const char *pnp);
@@ -91,9 +91,13 @@ tscmatch(device_t parent, cfdata_t match
{
struct mainbus_attach_args *ma = aux;
- return cputype == ST_DEC_6600
- && strcmp(ma->ma_name, tsc_cd.cd_name) == 0
- && !tscfound;
+ switch (cputype) {
+ case ST_DEC_6600:
+ case ST_DEC_TITAN:
+ return strcmp(ma->ma_name, tsc_cd.cd_name) == 0 && !tscfound;
+ default:
+ return 0;
+ }
}
static void
@@ -104,15 +108,16 @@ tscattach(device_t parent, device_t self
uint64_t csc, aar;
struct tsp_attach_args tsp;
struct mainbus_attach_args *ma = aux;
+ int titan = cputype == ST_DEC_TITAN;
tscfound = 1;
csc = LDQP(TS_C_CSC);
nbus = 1 + (CSC_BC(csc) >= 2);
- printf(": 21272 Core Logic Chipset, Cchip rev %d\n"
+ printf(": 2127%c Core Logic Chipset, Cchip rev %d\n"
"%s%d: %c Dchips, %d memory bus%s of %d bytes\n",
- (int)MISC_REV(LDQP(TS_C_MISC)),
+ titan ? '4' : '2', (int)MISC_REV(LDQP(TS_C_MISC)),
ma->ma_name, ma->ma_slot, "2448"[CSC_BC(csc)],
nbus, nbus > 1 ? "es" : "", 16 + 16 * ((csc & CSC_AW) != 0));
printf("%s%d: arrays present: ", ma->ma_name, ma->ma_slot);
@@ -125,11 +130,21 @@ tscattach(device_t parent, device_t self
memset(&tsp, 0, sizeof tsp);
tsp.tsp_name = "tsp";
- config_found(self, &tsp, NULL);
+ tsp.tsp_slot = 0;
+
+ config_found(self, &tsp, tscprint);
+ if (titan) {
+ tsp.tsp_slot += 2;
+ config_found(self, &tsp, tscprint);
+ }
- if(LDQP(TS_C_CSC) & CSC_P1P) {
- ++tsp.tsp_slot;
+ if (csc & CSC_P1P) {
+ tsp.tsp_slot = 1;
config_found(self, &tsp, tscprint);
+ if (titan) {
+ tsp.tsp_slot += 2;
+ config_found(self, &tsp, tscprint);
+ }
}
}
@@ -150,8 +165,13 @@ tspmatch(device_t parent, cfdata_t match
{
struct tsp_attach_args *t = aux;
- return cputype == ST_DEC_6600
- && strcmp(t->tsp_name, tsp_cd.cd_name) == 0;
+ switch (cputype) {
+ case ST_DEC_6600:
+ case ST_DEC_TITAN:
+ return strcmp(t->tsp_name, tsp_cd.cd_name) == 0;
+ default:
+ return 0;
+ }
}
static void
@@ -193,12 +213,24 @@ tsp_init(int mallocsafe, int n)
/* n: Pchip number */
{
struct tsp_config *pcp;
+ int titan = cputype == ST_DEC_TITAN;
- KASSERT((n | 1) == 1);
+ KASSERT(n >= 0 && n < __arraycount(tsp_configuration));
pcp = &tsp_configuration[n];
pcp->pc_pslot = n;
pcp->pc_iobase = TS_Pn(n, 0);
- pcp->pc_csr = S_PAGE(TS_Pn(n, P_CSRBASE));
+ pcp->pc_csr = S_PAGE(TS_Pn(n & 1, P_CSRBASE));
+ if (n & 2) {
+ /* `A' port of PA Chip */
+ pcp->pc_csr++;
+ }
+ if (titan) {
+ /* same address on G and A ports */
+ pcp->pc_tlbia = &pcp->pc_csr->port.g.tsp_tlbia.tsg_r;
+ } else {
+ pcp->pc_tlbia = &pcp->pc_csr->port.p.tsp_tlbia.tsg_r;
+ }
+
if (!pcp->pc_initted) {
tsp_bus_io_init(&pcp->pc_iot, pcp);
tsp_bus_mem_init(&pcp->pc_memt, pcp);
Index: pci/tsp_dma.c
===================================================================
RCS file: /cvsroot/src/sys/arch/alpha/pci/tsp_dma.c,v
retrieving revision 1.12
diff -u -p -r1.12 tsp_dma.c
--- pci/tsp_dma.c 6 Feb 2012 02:14:15 -0000 1.12
+++ pci/tsp_dma.c 16 Sep 2013 15:05:42 -0000
@@ -118,10 +118,10 @@ tsp_dma_init(struct tsp_config *pcp)
static struct map_expected {
uint32_t base, mask, enables;
} premap[4] = {
- { 0x800000, 0x700000, WSBA_ENA | WSBA_SG },
- { 0x80000000 | WSBA_ENA, 0x3ff00000, WSBA_ENA },
- { 0, 0 },
- { 0, 0 }
+ { 0x00800000, 0x00700000, WSBA_ENA | WSBA_SG },
+ { 0x80000000, 0x3ff00000, WSBA_ENA },
+ { 0, 0, 0 },
+ { 0, 0, 0 }
};
alpha_mb();
@@ -207,6 +207,14 @@ tsp_dma_init(struct tsp_config *pcp)
alpha_mb();
/*
+ * Enable window 1 in direct mode.
+ */
+ alpha_mb();
+ pccsr->tsp_wsba[1].tsg_r =
+ (pccsr->tsp_wsba[1].tsg_r & ~WSBA_SG) | WSBA_ENA;
+ alpha_mb();
+
+ /*
* Check windows for sanity, especially if we later decide to
* use the firmware's initialization in some cases.
*/
@@ -354,6 +362,6 @@ tsp_tlb_invalidate(struct tsp_config *pc
{
alpha_mb();
- pcp->pc_csr->tsp_tlbia.tsg_r = 0;
+ *pcp->pc_tlbia = 0;
alpha_mb();
}
Index: pci/tsreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/alpha/pci/tsreg.h,v
retrieving revision 1.5
diff -u -p -r1.5 tsreg.h
--- pci/tsreg.h 6 Feb 2012 02:14:15 -0000 1.5
+++ pci/tsreg.h 16 Sep 2013 15:05:42 -0000
@@ -186,7 +186,7 @@
*/
#define P_CSRBASE 0x001##8000##0000UL
-#define P_PCI_MEM 0
+#define P_PCI_MEM 0x800##0000##0000UL
#define P_PCI_IO 0x001##fc00##0000UL
#define P_PCI_CONFIG 0x001##fe00##0000UL
@@ -209,15 +209,7 @@ typedef struct _ts_gr {
/*
* Tsunami Pchip
*/
-struct ts_pchip {
- TS_GR tsp_wsba[4]; /* Window Space Base Address */
-
- TS_GR tsp_wsm[4]; /* Window Space Mask */
-
- TS_GR tsp_tba[4]; /* Translated Base Address */
-
- TS_GR tsp_pctl; /* Pchip Control */
- TS_GR tsp_plat; /* Pchip Latency */
+struct ts_pport {
TS_GR tsp_resA;
TS_GR tsp_error; /* Pchip Error */
@@ -232,6 +224,56 @@ struct ts_pchip {
TS_GR tsp_resC;
TS_GR tsp_resD_K[8];
+};
+
+struct ts_gport {
+ TS_GR tsp_resA[2];
+ TS_GR tsp_serror;
+ TS_GR tsp_serrmask;
+ TS_GR tsp_serrset;
+ TS_GR tsp_resB;
+ TS_GR tsp_gperrmask;
+ TS_GR tsp_gperren;
+ TS_GR tsp_gperrset;
+ TS_GR tsp_resC;
+ TS_GR tsp_tlbiv;
+ TS_GR tsp_tlbia;
+ TS_GR tsp_resD[2];
+ TS_GR tsp_sctl;
+ TS_GR tsp_resE[3];
+};
+
+struct ts_aport {
+ TS_GR tsp_resA[2];
+ TS_GR tsp_agperror;
+ TS_GR tsp_agperrmask;
+ TS_GR tsp_agperrset;
+ TS_GR tsp_agplastwr;
+ TS_GR tsp_aperror;
+ TS_GR tsp_aperrmask;
+ TS_GR tsp_aperrset;
+ TS_GR tsp_resB;
+ TS_GR tsp_tlbiv;
+ TS_GR tsp_tlbia;
+ TS_GR tsp_resC[6];
+};
+
+struct ts_pchip {
+ TS_GR tsp_wsba[4]; /* Window Space Base Address */
+
+ TS_GR tsp_wsm[4]; /* Window Space Mask */
+
+ TS_GR tsp_tba[4]; /* Translated Base Address */
+
+ TS_GR tsp_pctl; /* Pchip Control */
+ TS_GR tsp_plat; /* Pchip Latency */
+
+ union {
+ struct ts_pport p;
+ struct ts_gport g;
+ struct ts_aport a;
+ } port;
TS_GR tsp_sprts; /* ??? */
+ TS_GR tsp_res[31];
};
Index: pci/tsvar.h
===================================================================
RCS file: /cvsroot/src/sys/arch/alpha/pci/tsvar.h,v
retrieving revision 1.10
diff -u -p -r1.10 tsvar.h
--- pci/tsvar.h 6 Feb 2012 02:14:15 -0000 1.10
+++ pci/tsvar.h 16 Sep 2013 15:05:42 -0000
@@ -44,6 +44,7 @@ struct tsp_config {
int pc_initted; /* Initialized */
uint64_t pc_iobase; /* All Pchip space starts here */
struct ts_pchip *pc_csr; /* Pchip CSR space starts here */
+ volatile uint64_t *pc_tlbia; /* Pchip TLBIA register address */
struct alpha_bus_space pc_iot, pc_memt;
struct alpha_pci_chipset pc_pc;
---
More notes from discussion with the submitter:
> tsp0 at tsc0
> pci0 at tsp0 bus 0
:
> tsp1 at tsc0
> pci1 at tsp1 bus 0
As seen in dmesg, DS15 (and other Tsunami based systems including XP1000)
have two PCI busses (without bridges).
We need more fixes to support DMA xfers and interrupts for
the second PCI bus:
- handle more than one PCI DMA direct mappings (see bus_dma(9) paper)
- prepare proper interrupt mappings for the second PCI
Note Linux has the following code for Tsunami:
http://lxr.linux.no/#linux+v3.11.1/arch/alpha/kernel/sys_titan.c
http://lxr.linux.no/#linux+v3.11.1/arch/alpha/kernel/setup.c#L963
---
Izumi Tsutsui
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