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Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA VT-310DP motherboard


Unfortunately I didn't get any response to my last message so I
debugged the system a little bit more... There is some small
information that I missed previous times and can be helpful. I booted
the system with debug messages (-vx) and got a bit more information.
Firstly I received x86_ipi_init: ESR 00000040 message (it is from
lapic.c x86_ipi_init function and target value equals 1). It means
that IPI with illegal vector was received by Intel APIC specification.
Maybe this is the point where the problem began? It happens before
cpu_start_secondary and subsequently tsc_read_bp is executed (where
I'm getting infinitive loop). Secondly, I also compared various values
between correctly working system (dual core Athlon II X2) and VT-310DP
in tsc_read_bp function during execution. It seems that these values
were set correctly except that tsc_sync_cpu never becomes null on
VT-310DP. I used quite recent NetBSD-current for tests so the problem
remains in current version. Here is updated boot log with debug

Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007, 2008, 2009, 2010, 2011
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 5.99.48 (GENERIC) #0: Sun Mar 20 11:14:49 UTC 2011
total memory = 1981 MB
avail memory = 1935 MB
Prep module path=ffs len=230310 pa=c4d000
timecounter: Timecounters tick every 10.000 msec
timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
BIOS32 rev. 0 found at 0xfa2a0
SMBIOS rev. 2.3 @ 0xf0000 (37 entries)
VIA Technologies, Inc. CN400-8237 ( )
mainbus0 (root)
cpu0 at mainbus0 apid 0cpu0: calibrating local timer
cpu0: apic clock running at 133 MHz
timecounter: Timecounter "lapic" frequency 133032744 Hz quality -100
: VIA Nehemiah, id 0x69a
cpu0: PAT enabled
cpu1 at mainbus0 apid 1x86_ipi_init: ESR 00000040

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