Re: port-i386/44581: MacBook1,1 won't resume after suspend

[Taylor R Campbell <campbell+netbsd%mumble.net@localhost>]

The following reply was made to PR port-i386/44581; it has been noted by GNATS.

From: Taylor R Campbell <campbell+netbsd%mumble.net@localhost>
To: gnats-bugs%NetBSD.org@localhost
Cc: 
Subject: Re: port-i386/44581: MacBook1,1 won't resume after suspend
Date: Wed, 16 Feb 2011 17:50:14 +0000

 Here's a diff between the outputs of `pcictl pci3 dump -d 3 -f 0'
 (where fwohci0 attaches), before and after suspending & resuming.
 This probably explains why fwohci0 fails after resumption.  Perhaps
 someone who is better versed in PCI than I am can interpret it and
 figure out what went wrong faster than I can.
 
 The relevant part of the configuration looks like
 
 root -> mainbus0 -> pci0 -> ppb2 -> pci3 -> fwohci0.
 
 --- pci3dump.0.boot    2011-02-16 17:08:02.000000000 +0000
 +++ pci3dump.2.resumed 2011-02-16 17:09:36.000000000 +0000
 @@ -1,20 +1,20 @@
  PCI configuration registers:
    Common header:
 -    0x00: 0x581111c1 0x02900216 0x0c001061 0x0000f810
 +    0x00: 0x581111c1 0x02900000 0x0c001061 0x00000000
  
      Vendor Name: Lucent Technologies (0x11c1)
      Device Name: FW322/323 IEEE 1394 Host Controller (0x5811)
 -    Command register: 0x0216
 +    Command register: 0x0000
        I/O space accesses: off
 -      Memory space accesses: on
 -      Bus mastering: on
 +      Memory space accesses: off
 +      Bus mastering: off
        Special cycles: off
 -      MWI transactions: on
 +      MWI transactions: off
        Palette snooping: off
        Parity error checking: off
        Address/data stepping: off
        System error (SERR): off
 -      Fast back-to-back transactions: on
 +      Fast back-to-back transactions: off
        Interrupt disable: off
      Status register: 0x0290
        Capability List support: on
 @@ -34,17 +34,16 @@
      Revision ID: 0x61
      BIST: 0x00
      Header Type: 0x00 (0x00)
 -    Latency Timer: 0xf8
 -    Cache Line Size: 0x10
 +    Latency Timer: 0x00
 +    Cache Line Size: 0x00
  
    Type 0 ("normal" device) header:
 -    0x10: 0x90000000 0x00000000 0x00000000 0x00000000
 +    0x10: 0x00000000 0x00000000 0x00000000 0x00000000
      0x20: 0x00000000 0x00000000 0x00000000 0x581111c1
 -    0x30: 0x00000000 0x00000044 0x00000000 0x180c010b
 +    0x30: 0x00000000 0x00000044 0x00000000 0x180c0100
  
      Base address register at 0x10
 -      type: 32-bit nonprefetchable memory
 -      base: 0x90000000, not sized
 +      not implemented(?)
      Base address register at 0x14
        not implemented(?)
      Base address register at 0x18
 @@ -64,7 +63,7 @@
      Maximum Latency: 0x18
      Minimum Grant: 0x0c
      Interrupt pin: 0x01 (pin A)
 -    Interrupt line: 0x0b
 +    Interrupt line: 0x00
  
    Capability register at 0x44
      type: 0x01 (Power Management, rev. 1.0)
 @@ -78,15 +77,15 @@
        D1 power management state support: on
        D2 power management state support: on
        PME# support: 0x0f
 -    Control/status register: 0x8000
 +    Control/status register: 0x0000
        Power state: D0
        PCI Express reserved: off
        No soft reset: off
        PME# assertion disabled
 -      PME# status: on
 +      PME# status: off
  
    Device-dependent header:
 -    0x40: 0x00000000 0x7e020001 0x00008000 0x00000000
 +    0x40: 0x00000000 0x7e020001 0x00000000 0x00000000
      0x50: 0x00000000 0x00000000 0x00000000 0x00000000
      0x60: 0x00000000 0x00000000 0x00000000 0x00000000
      0x70: 0x........ 0x........ 0x00000000 0x00000000