NetBSD-Bugs archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

kern/44080: Support for the i82577 ethernet PHY



>Number:         44080
>Category:       kern
>Synopsis:       Support for the i82577 ethernet PHY
>Confidential:   no
>Severity:       non-critical
>Priority:       medium
>Responsible:    kern-bug-people
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Wed Nov 10 22:50:01 +0000 2010
>Originator:     Grégoire Sutre
>Release:        NetBSD 5.99.39 (20101031)
>Organization:
>Environment:
System: NetBSD yosemite 5.99.39 NetBSD 5.99.39 (GENERIC) #1: Wed Nov 10 
17:16:19 CET 2010 
sutre@tahoe:/data/sutre/build-amd64/home/sutre/netbsd/src/sys/arch/amd64/compile/GENERIC
 amd64
Architecture: x86_64
Machine: amd64
>Description:

The Intel 82577 ethernet PHY is not correctly handled by the ukphy(4)
driver.  The following is on a Dell E4310 with -current, and others
obtain similar logs [1, 2]:

wm0 at pci0 dev 25 function 0: PCH LAN (82577LM) Controller, rev. 5
wm0: interrupting at ioapic0 pin 20
wm0: PCI-Express bus
wm0: FLASH
wm0: Ethernet address 5c:26:0a:13:8f:e1
ukphy0 at wm0 phy 2: OUI 0x00aa00, model 0x0005, rev. 3
ukphy0: no media present
ifmedia_set: no match for 0x20/0xfffffff

[1] http://mail-index.netbsd.org/current-users/2010/08/20/msg014129.html
[2] http://mail-index.netbsd.org/current-users/2010/10/01/msg014446.html

As noted in [2], the problem comes from the reset operation.  A few
debug printfs show that, after a reset, the bit BMCR_RESET is cleared
immediately, but the reset is not complete yet: the status register
reads as zero for a couple milliseconds.

In fact, the data sheet says that one should wait 10ms after a PHY
reset before any other register access.

>How-To-Repeat:

Boot a -current kernel on a machine with an i82577 ethernet PHY.

>Fix:

Adding 10ms delay in the mii_phy_reset() function is sufficient to
solve this problem.  But, while there, I wrote a driver for this PHY.
The driver, called ihphy, is inspired from the ukphy(4) driver, and
from the existing Intel PHY drivers.  For the PHY experts, the main
changes w.r.t. to these drivers are the following:

- a reset() function that integrates the required 10ms delay.

- in attach(), vendor-specific registers are set to match what is done
  in Intel's Linux driver for the 82577.

- in service(),
  . case MII_MEDIACHG: the link is (effectively) disabled for IFM_NONE
    via a vendor-specific register.
  . case MII_DOWN: the PHY is powered down by setting the BMCR_PDOWN
    bit of the standard control register.

- in status(), vendor-specific registers are used to read the link
  status and speed, and they are used even if auto-negotiation is
  disabled.  Moreover, if the PHY is powered down, we behave in the
  same way as when the PHY is isolated.

Since I am not a PHY expert myself, feedback and corrections are most
welcome.

Grégoire

Index: files.mii
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/files.mii,v
retrieving revision 1.45
diff -u -p -r1.45 files.mii
--- files.mii   30 May 2010 17:44:08 -0000      1.45
+++ files.mii   10 Nov 2010 22:31:10 -0000
@@ -136,3 +136,7 @@ file        dev/mii/mvphy.c                         mvphy
 device atphy: mii_phy
 attach atphy at mii
 file   dev/mii/atphy.c                         atphy
+
+device ihphy: mii_phy
+attach ihphy at mii
+file   dev/mii/ihphy.c                         ihphy
Index: ihphy.c
===================================================================
RCS file: ihphy.c
diff -N ihphy.c
--- /dev/null   1 Jan 1970 00:00:00 -0000
+++ ihphy.c     10 Nov 2010 22:31:10 -0000
@@ -0,0 +1,324 @@
+/*     $NetBSD: $      */
+
+/*-
+ * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center, and by Frank van der Linden.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for Intel's 82577 (Hanksville) Ethernet 10/100/1000 PHY
+ * Data Sheet: http://download.intel.com/design/network/datashts/319439.pdf
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+#include <sys/errno.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/mii/miidevs.h>
+
+#include <dev/mii/ihphyreg.h>
+
+static int     ihphymatch(device_t, cfdata_t, void *);
+static void    ihphyattach(device_t, device_t, void *);
+
+CFATTACH_DECL3_NEW(ihphy, sizeof(struct mii_softc),
+    ihphymatch, ihphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL,
+    DVF_DETACH_SHUTDOWN);
+
+static int     ihphy_service(struct mii_softc *, struct mii_data *, int);
+static void    ihphy_status(struct mii_softc *);
+static void    ihphy_reset(struct mii_softc *);
+
+static const struct mii_phy_funcs ihphy_funcs = {
+       ihphy_service, ihphy_status, ihphy_reset,
+};
+
+static const struct mii_phydesc ihphys[] = {
+       { MII_OUI_INTEL,                MII_MODEL_INTEL_I82577,
+         MII_STR_INTEL_I82577 },
+
+       { 0,                            0,
+         NULL },
+};
+
+static int
+ihphymatch(device_t parent, cfdata_t match, void *aux)
+{
+       struct mii_attach_args *ma = aux;
+
+       if (mii_phy_match(ma, ihphys) != NULL)
+               return (10);
+
+       return (0);
+}
+
+static void
+ihphyattach(device_t parent, device_t self, void *aux)
+{
+       struct mii_softc *sc = device_private(self);
+       struct mii_attach_args *ma = aux;
+       struct mii_data *mii = ma->mii_data;
+       const struct mii_phydesc *mpd;
+       int reg;
+
+       mpd = mii_phy_match(ma, ihphys);
+       aprint_naive(": Media interface\n");
+       aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
+
+       sc->mii_dev = self;
+       sc->mii_inst = mii->mii_instance;
+       sc->mii_phy = ma->mii_phyno;
+       sc->mii_funcs = &ihphy_funcs;
+       sc->mii_pdata = mii;
+       sc->mii_flags = ma->mii_flags;
+       sc->mii_anegticks = MII_ANEGTICKS;
+
+       PHY_RESET(sc);
+
+       sc->mii_capabilities =
+           PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
+       if (sc->mii_capabilities & BMSR_EXTSTAT)
+               sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
+       aprint_normal_dev(self, "");
+       if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
+           (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
+               aprint_error("no media present");
+       else
+               mii_phy_add_media(sc);
+       aprint_normal("\n");
+
+       /*
+        * Link setup (as done by Intel's Linux driver for the 82577).
+        */
+       reg = PHY_READ(sc, IHPHY_MII_CFG);
+       reg |= IHPHY_CFG_TX_CRS;
+       reg |= IHPHY_CFG_DOWN_SHIFT;
+       PHY_WRITE(sc, IHPHY_MII_CFG, reg);
+}
+
+static int
+ihphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
+{
+       struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+       int reg;
+
+       switch (cmd) {
+       case MII_POLLSTAT:
+               /*
+                * If we're not polling our PHY instance, just return.
+                */
+               if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+                       return (0);
+               break;
+
+       case MII_MEDIACHG:
+               /*
+                * If the media indicates a different PHY instance,
+                * isolate ourselves.
+                */
+               if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
+                       reg = PHY_READ(sc, MII_BMCR);
+                       PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
+                       return (0);
+               }
+
+               /*
+                * If the interface is not up, don't do anything.
+                */
+               if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+                       break;
+
+               /*
+                * If media is deselected, disable link (standby).
+                */
+               reg = PHY_READ(sc, IHPHY_MII_ECR);
+               if (IFM_SUBTYPE(ife->ifm_media) == IFM_NONE)
+                       reg &= ~IHPHY_ECR_LNK_EN;
+               else
+                       reg |= IHPHY_ECR_LNK_EN;
+               PHY_WRITE(sc, IHPHY_MII_ECR, reg);
+
+               /*
+                * XXX Adjust MDI/MDIX configuration?  Other settings?
+                */
+
+               mii_phy_setmedia(sc);
+               break;
+
+       case MII_TICK:
+               /*
+                * If we're not currently selected, just return.
+                */
+               if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+                       return (0);
+
+               /*
+                * Only used for autonegotiation.
+                */
+               if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
+                       return (0);
+
+               if (mii_phy_tick(sc) == EJUSTRETURN)
+                       return (0);
+               break;
+
+       case MII_DOWN:
+               mii_phy_down(sc);
+               PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN);
+               return (0);
+       }
+
+       /* Update the media status. */
+       mii_phy_status(sc);
+
+       /* Callback if something changed. */
+       mii_phy_update(sc, cmd);
+       return (0);
+}
+
+static void
+ihphy_status(struct mii_softc *sc)
+{
+       struct mii_data *mii = sc->mii_pdata;
+       int esr, bmcr, gtsr;
+
+       mii->mii_media_status = IFM_AVALID;
+       mii->mii_media_active = IFM_ETHER;
+
+       esr = PHY_READ(sc, IHPHY_MII_ESR);
+
+       if (esr & IHPHY_ESR_LINK)
+               mii->mii_media_status |= IFM_ACTIVE;
+
+       bmcr = PHY_READ(sc, MII_BMCR);
+       if (bmcr & (BMCR_ISO | BMCR_PDOWN)) {
+               mii->mii_media_active |= IFM_NONE;
+               mii->mii_media_status = 0;
+               return;
+       }
+
+       if (bmcr & BMCR_LOOP)
+               mii->mii_media_active |= IFM_LOOP;
+
+       if (bmcr & BMCR_AUTOEN) {
+               if ((esr & IHPHY_ESR_ANEG_STAT) == 0) {
+                       /* Erg, still trying, I guess... */
+                       mii->mii_media_active |= IFM_NONE;
+                       return;
+               }
+       }
+
+       switch (esr & IHPHY_ESR_SPEED) {
+       case IHPHY_SPEED_1000:
+               mii->mii_media_active |= IFM_1000_T;
+               gtsr = PHY_READ(sc, MII_100T2SR);
+               if (gtsr & GTSR_MS_RES)
+                       mii->mii_media_active |= IFM_ETH_MASTER;
+               break;
+
+       case IHPHY_SPEED_100:
+               /* 100BASE-T2 and 100BASE-T4 are not supported. */
+               mii->mii_media_active |= IFM_100_TX;
+               break;
+
+       case IHPHY_SPEED_10:
+               mii->mii_media_active |= IFM_10_T;
+               break;
+
+       default:
+               mii->mii_media_active |= IFM_NONE;
+               mii->mii_media_status = 0;
+               return;
+       }
+
+       if (esr & IHPHY_ESR_DUPLEX)
+               mii->mii_media_active |=
+                   IFM_FDX | mii_phy_flowstatus(sc);
+}
+
+static void
+ihphy_reset(struct mii_softc *sc)
+{
+       int reg, i;
+
+       PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_ISO);
+
+       /*
+        * Regarding reset, the data sheet specifies (page 55):
+        *
+        * "After PHY reset, a delay of 10 ms is required before
+        *  any register access using MDIO."
+        */
+       delay(10000);
+
+       /* Wait another 100ms for it to complete. */
+       for (i = 0; i < 100; i++) {
+               reg = PHY_READ(sc, MII_BMCR);
+               if ((reg & BMCR_RESET) == 0)
+                       break;
+               delay(1000);
+       }
+
+       if (sc->mii_inst != 0)
+               PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
+}
Index: ihphyreg.h
===================================================================
RCS file: ihphyreg.h
diff -N ihphyreg.h
--- /dev/null   1 Jan 1970 00:00:00 -0000
+++ ihphyreg.h  10 Nov 2010 22:31:10 -0000
@@ -0,0 +1,111 @@
+/*     $NetBSD: $      */
+
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_MII_IHPHYREG_H_
+#define        _DEV_MII_IHPHYREG_H_
+
+#include <dev/mii/inbmphyreg.h>
+
+/*
+ * Intel 82577LM registers.
+ */
+
+/* PHY Control Register 2 */
+#define        IHPHY_MII_ECR2          BME1000_REG(0, 18)
+
+/* Loopback Control Register */
+#define        IHPHY_MII_LCR           BME1000_REG(0, 19)
+
+/* RX Error Counter Register */
+#define        IHPHY_MII_RXERR         BME1000_REG(0, 20)
+
+/* Management Interface Register */
+#define        IHPHY_MII_MIR           BME1000_REG(0, 21)
+
+/* PHY Configuration Register */
+#define        IHPHY_MII_CFG           BME1000_REG(0, 22)
+#define        IHPHY_CFG_TX_CRS        0x8000  /* CRS transmit enable */
+#define        IHPHY_CFG_FIFO_DEPTH    0x3000  /* Transmit FIFO depth*/
+#define        IHPHY_CFG_DOWN_SHIFT    0x0C00  /* Automatic speed downshift 
mode */
+#define        IHPHY_CFG_ALT_PAGE      0x0080  /* Alternate next page */
+#define        IHPHY_CFG_GRP_MDIO      0x0040  /* Group MDIO mode enable */
+#define        IHPHY_CFG_TX_CLOCK      0x0020  /* Transmit clock enable */
+
+/* PHY Control Register */
+#define        IHPHY_MII_ECR           BME1000_REG(0, 23)
+#define        IHPHY_ECR_LNK_EN        0x2000  /* Link enable */
+#define        IHPHY_ECR_DOWN_SHIFT    0x1C00  /* Automatic speed downshift 
attempts */
+#define        IHPHY_ECR_LNK_PARTNER   0x0080  /* Link Partner Detected */
+#define        IHPHY_ECR_JABBER        0x0040  /* Jabber (10BASE-T) */
+#define        IHPHY_ECR_SQE           0x0020  /* Heartbeat (10BASE-T) */
+#define        IHPHY_ECR_TP_LOOPBACK   0x0010  /* TP loopback (10BASE-T) */
+#define        IHPHY_ECR_PRE_LENGTH    0x000C  /* Preamble length (10BASE-T) */
+
+/* Interrupt Mask Register */
+#define        IHPHY_MII_IMR           BME1000_REG(0, 24)
+
+/* Interrupt Status Register */
+#define        IHPHY_MII_ISR           BME1000_REG(0, 25)
+
+/* PHY Status Register */
+#define        IHPHY_MII_ESR           BME1000_REG(0, 26)
+#define        IHPHY_ESR_STANDBY       0x8000  /* PHY in standby */
+#define        IHPHY_ESR_ANEG_FAULT    0x6000  /* Autonegotation fault status 
*/
+#define        IHPHY_ESR_ANEG_STAT     0x1000  /* Autonegotiation status */
+#define        IHPHY_ESR_PAIR_SWAP     0x0800  /* Pair swap on pairs A and B */
+#define        IHPHY_ESR_POLARITY      0x0400  /* Polarity status */
+#define        IHPHY_ESR_SPEED         0x0300  /* Speed status */
+#define        IHPHY_ESR_DUPLEX        0x0080  /* Duplex status */
+#define        IHPHY_ESR_LINK          0x0040  /* Link status */
+#define        IHPHY_ESR_TRANSMIT      0x0020  /* Transmit status */
+#define        IHPHY_ESR_RECEIVE       0x0010  /* Receive status */
+#define        IHPHY_ESR_COLLISION     0x0008  /* Collision status */
+#define        IHPHY_ESR_ANEG_BOTH     0x0004  /* Autonegotiation enabled for 
both */
+#define        IHPHY_ESR_PAUSE         0x0002  /* Link partner has PAUSE */
+#define        IHPHY_ESR_ASYM_PAUSE    0x0001  /* Link partner has asymmetric 
PAUSE */
+
+#define IHPHY_SPEED_10         0x0000
+#define IHPHY_SPEED_100                0x0100
+#define IHPHY_SPEED_1000       0x0200
+
+/* LED Control Register 1 */
+#define        IHPHY_MII_LED1          BME1000_REG(0, 27)
+
+/* LED Control Register 2 */
+#define        IHPHY_MII_LED2          BME1000_REG(0, 28)
+
+/* LED Control Register 3 */
+#define        IHPHY_MII_LED3          BME1000_REG(0, 29)
+
+/* Diagnostics Control Register */
+#define        IHPHY_MII_DCR           BME1000_REG(0, 30)
+
+/* Diagnostics Status Register */
+#define        IHPHY_MII_DSR           BME1000_REG(0, 31)
+
+#endif /* _DEV_IHPHY_MIIREG_H_ */
Index: miidevs
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/miidevs,v
retrieving revision 1.95
diff -u -p -r1.95 miidevs
--- miidevs     2 May 2010 12:38:06 -0000       1.95
+++ miidevs     10 Nov 2010 22:31:10 -0000
@@ -207,6 +207,7 @@ model yyINTEL I82562EM              0x0032 i82562EM 
 model yyINTEL I82562ET         0x0033 i82562ET 10/100 media interface
 model yyINTEL I82553           0x0035 i82553 10/100 media interface
 model yyINTEL I82566           0x0039 i82566 10/100/1000 media interface
+model INTEL I82577             0x0005 i82577 10/100/1000 media interface
 model xxMARVELL I82563         0x000a i82563 10/100/1000 media interface
 
 model yyINTEL IGP01E1000       0x0038 Intel IGP01E1000 Gigabit PHY
Index: miidevs.h
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/miidevs.h,v
retrieving revision 1.97
diff -u -p -r1.97 miidevs.h
--- miidevs.h   2 May 2010 12:43:05 -0000       1.97
+++ miidevs.h   10 Nov 2010 22:31:10 -0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: miidevs.h,v 1.97 2010/05/02 12:43:05 pgoyette Exp $    */
+/*     $NetBSD$        */
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
@@ -286,6 +286,8 @@
 #define        MII_STR_yyINTEL_I82553  "i82553 10/100 media interface"
 #define        MII_MODEL_yyINTEL_I82566        0x0039
 #define        MII_STR_yyINTEL_I82566  "i82566 10/100/1000 media interface"
+#define        MII_MODEL_INTEL_I82577  0x0005
+#define        MII_STR_INTEL_I82577    "i82577 10/100/1000 media interface"
 #define        MII_MODEL_xxMARVELL_I82563      0x000a
 #define        MII_STR_xxMARVELL_I82563        "i82563 10/100/1000 media 
interface"
 
Index: miidevs_data.h
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/miidevs_data.h,v
retrieving revision 1.86
diff -u -p -r1.86 miidevs_data.h
--- miidevs_data.h      2 May 2010 12:43:05 -0000       1.86
+++ miidevs_data.h      10 Nov 2010 22:31:10 -0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: miidevs_data.h,v 1.86 2010/05/02 12:43:05 pgoyette Exp $       
*/
+/*     $NetBSD$        */
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
@@ -109,6 +109,7 @@ struct mii_knowndev mii_knowndevs[] = {
  { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82562ET, MII_STR_yyINTEL_I82562ET },
  { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82553, MII_STR_yyINTEL_I82553 },
  { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82566, MII_STR_yyINTEL_I82566 },
+ { MII_OUI_INTEL, MII_MODEL_INTEL_I82577, MII_STR_INTEL_I82577 },
  { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_I82563, MII_STR_xxMARVELL_I82563 },
  { MII_OUI_yyINTEL, MII_MODEL_yyINTEL_IGP01E1000, MII_STR_yyINTEL_IGP01E1000 },
  { MII_OUI_JMICRON, MII_MODEL_JMICRON_JMC250, MII_STR_JMICRON_JMC250 },



Home | Main Index | Thread Index | Old Index