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Re: port-amd64/42597: LAPIC MSR address mask 4 bits short
The following reply was made to PR port-amd64/42597; it has been noted by GNATS.
Subject: Re: port-amd64/42597: LAPIC MSR address mask 4 bits short
Date: Sun, 10 Jan 2010 12:03:56 +1100
Yeah, the MSR's are read using special instructions, specifically using
the assembly routines rdmsr and wrmsr where hi 32 bits are in rdx and
low 32 bits in rax. The Intel documentation doesn't mention any
variations to this instruction for all 64 and IA-32 platform's, other
than on models which don't have the instructions in the first place.
I overlooked the i386 aspects of my suggested change and I see that it
is not quite so straight forward. On standard i386 platform's i guess
that the upper 4 bits past 32 are not relevant for addressing. When
running, say PAE, where the address space is bigger might allow for
such possible addresses of an APIC.
A little more thought required here...
> The following reply was made to PR port-amd64/42597; it has been noted by
> From: David Laight <david%l8s.co.uk@localhost>
> To: gnats-bugs%NetBSD.org@localhost
> Cc: port-amd64-maintainer%netbsd.org@localhost,
> Subject: Re: port-amd64/42597: LAPIC MSR address mask 4 bits short
> Date: Sat, 9 Jan 2010 11:33:49 +0000
> On Sat, Jan 09, 2010 at 10:40:01AM +0000, murray%river-styx.org@localhost
> > # define LAPIC_MSR_ENABLE 0x00000800 /* software
> enable */
> > -# define LAPIC_MSR_ADDR 0xfffff000 /* physical
> address */
> > +# define LAPIC_MSR_ADDR 0xffffff000 /* physical
> address */
> That value is out of range for an integer constant.
> I'd have to read the docs, but aren't the MSRs accessed using special
> instructions - do that have > 32 bits physical address, especially on
> David Laight: david%l8s.co.uk@localhost
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