port-amd64/42597: LAPIC MSR address mask 4 bits short

[murray%river-styx.org@localhost]

>Number:         42597
>Category:       port-amd64
>Synopsis:       LAPIC MSR address mask 4 bits short
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    port-amd64-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Sat Jan 09 10:40:00 +0000 2010
>Originator:     Murray Armfield
>Release:        NetBSD-current
>Organization:
N/A
>Environment:
N/A
>Description:
The Intel 64 and IA32 Architectures Software Developer's Manual Vol 3A in 
chapter 10.4.4 states that the APIC Base field component of the IA32_APIC_BASE 
MSR uses bits 12 through to 35. This translates to an address mask of 
0xffffff000. (6 f's)

The address mask found in current sources, file 
sys/arch/x86/include/i82489reg.h line 153 defines LAPIC_MSR_ADDR as 0xfffff000 
(5 f's).

This is 4 bits short of the possible address mask. The IA32_APIC_BASE MSR is 64 
bits wide.
>How-To-Repeat:
Code inspection & read the Intel documentation
>Fix:
--- sys/arch/x86/include/i82489reg.h.orig       2010-01-09 10:36:06.000000000 
+0000
+++ sys/arch/x86/include/i82489reg.h
@@ -150,5 +150,5 @@
 #define        LAPIC_MSR       0x001b
 #      define  LAPIC_MSR_BSP           0x00000100      /* boot processor */
 #      define  LAPIC_MSR_ENABLE        0x00000800      /* software enable */
-#      define  LAPIC_MSR_ADDR          0xfffff000      /* physical address */
+#      define  LAPIC_MSR_ADDR          0xffffff000     /* physical address */