Re: port-hp700/35531: iee0 does not work on 735/99

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

The following reply was made to PR port-hp700/35531; it has been noted by GNATS.

From: Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>
To: nick.hudson%gmx.co.uk@localhost
Cc: gnats-bugs%NetBSD.org@localhost, port-hp700-maintainer%NetBSD.org@localhost,
        gnats-admin%NetBSD.org@localhost, netbsd-bugs%NetBSD.org@localhost, 
root%garbled.net@localhost,
        tsutsui%ceres.dti.ne.jp@localhost
Subject: Re: port-hp700/35531: iee0 does not work on 735/99
Date: Wed, 6 May 2009 03:15:19 +0900

 I wrote:
 
 > I wrote:
 > > nick.hudson%gmx.co.uk@localhost wrote:
 > > > I've tested this on my 715/50 against netbsd-5 as I've got too many 
 > > > changes in 
 > > > my -current source trees :)
 > > 
 > > The same patch can be applied to -current too ;-)
 > 
 > Umm, on -current iee(4) even without my patch gets
 > timeouts and errors on heavy load:
 
 Okay, this is DMA-cache coherency problem. bus_dma(9) on hp700
 doesn't support BUS_DMA_COHERENT even on any CPU, so we have to
 always set proper cache line size to sc_cl_align for MI iee(4).
 (probably it might be worth to have <machine/cache.h> like mips)
 
 ---
 Index: if_iee_gsc.c
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/hp700/gsc/if_iee_gsc.c,v
 retrieving revision 1.8
 diff -u -r1.8 if_iee_gsc.c
 --- if_iee_gsc.c       30 Apr 2009 07:01:26 -0000      1.8
 +++ if_iee_gsc.c       5 May 2009 18:10:11 -0000
 @@ -206,9 +206,9 @@
        struct iee_gsc_softc *sc_gsc = device_private(self);
        struct iee_softc *sc = &sc_gsc->iee_sc;
        struct gsc_attach_args *ga = aux;
 -      enum hppa_cpu_type cpu_type;
        int media[2];
        int rsegs;
 +      extern int dcache_stride;       /* XXX: in hp700/machdep.c */
  
        sc->sc_dev = self;
  
 @@ -221,12 +221,11 @@
         * Pre PA7100LC CPUs don't support uncacheable mappings. So make 
         * descriptors align to cache lines. Needed to avoid race conditions 
         * caused by flushing cache lines that overlap multiple descriptors. 
 +       *
 +       * XXX: MD bus_dma(9) on hp700 doesn't support BUS_DMA_COHERENT at all,
 +       *      so use dcache_stride on all CPUs for now.
         */
 -        cpu_type = hppa_cpu_info->hci_type;
 -      if (cpu_type == hpcx || cpu_type == hpcxs || cpu_type == hpcxt)
 -              sc->sc_cl_align = 32;
 -      else
 -              sc->sc_cl_align = 1;
 +      sc->sc_cl_align = dcache_stride;
  
        sc_gsc->sc_iot = ga->ga_iot;
        if (bus_space_map(sc_gsc->sc_iot, ga->ga_hpa, IEE_GSC_IO_SZ, 0, 
 
 ---
 Izumi Tsutsui