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Re: port-sgimips/38932: sgimips bus_dmamap_sync() is incorrect
On Wed, Jun 11, 2008 at 05:05:50AM +0900, Izumi Tsutsui wrote:
> > I see your point. But I'm not sure such devices can work reliably
> > with a write-back cache if regions are not cacheline-aligned.
> > For example, I'm almost sure an uchi/ehci can't work reliably on hosts
> > with write-back caches (unless the descriptors are mappped uncached).
> > I suspect re(4) has the same issue with re_desc->re_cmdstat (the updated
> > re_cmdstat from a descriptor may be lost if the host writes another
> > descriptor in the same cache line).
> Yes, ideally we can allocate only one descriptor per each cacheline
> to avoid race, but not all devices (for PC) assume such hardware.
> In such case, BUS_DMA_COHERENT is mandatory.
> But anyway we can't invalidate cache in POSTREAD/POSTWRITE
> because they have the same problems even on data xfers.
On second though I think you're right on this. Please close the PR.
Manuel Bouyer <bouyer%antioche.eu.org@localhost>
NetBSD: 26 ans d'experience feront toujours la difference
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