Subject: Re: port-mips/31915: provide centralized wired_map logic
To: None <port-mips-maintainer@netbsd.org, gnats-admin@netbsd.org,>
From: Garrett D'Amore <garrett_damore@tadpole.com>
List: netbsd-bugs
Date: 10/25/2005 20:54:02
The following reply was made to PR port-mips/31915; it has been noted by GNATS.
From: "Garrett D'Amore" <garrett_damore@tadpole.com>
To: gnats-bugs@netbsd.org
Cc:
Subject: Re: port-mips/31915: provide centralized wired_map logic
Date: Tue, 25 Oct 2005 13:53:14 -0700
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Here are the diffs. Again, I've not conditionalized the inclusion of
mips3_wired_map.c, but if folks feel strongly enough about it I can
certainly do so.
Also, the ARC port could probably make use of my logic in
mips3_wired_map.c, but I wanted to minimize change (and I don't have an
ARC system to test against, anyway, so all I can do is verify the compile.)
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Index: sys/arch/mips/conf/files.mips
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/conf/files.mips,v
retrieving revision 1.1.1.1
retrieving revision 1.4
diff -c -r1.1.1.1 -r1.4
*** sys/arch/mips/conf/files.mips 29 Sep 2005 16:42:46 -0000 1.1.1.1
--- sys/arch/mips/conf/files.mips 25 Oct 2005 20:49:31 -0000 1.4
***************
*** 37,42 ****
--- 37,43 ----
file arch/mips/mips/vm_machdep.c
file arch/mips/mips/process_machdep.c
file arch/mips/mips/cpu_exec.c
+ file arch/mips/mips/mips3_wired_map.c !mips1
file arch/mips/mips/cache.c
file arch/mips/mips/cache_r3k.c mips1
Index: sys/arch/mips/mips/mipsX_subr.S
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/mips/mipsX_subr.S,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -c -r1.1.1.1 -r1.2
*** sys/arch/mips/mips/mipsX_subr.S 29 Sep 2005 16:42:52 -0000 1.1.1.1
--- sys/arch/mips/mips/mipsX_subr.S 24 Oct 2005 22:06:38 -0000 1.2
***************
*** 1595,1600 ****
--- 1595,1651 ----
/*--------------------------------------------------------------------------
*
+ * mipsN_TLBWriteIndexedVPS --
+ *
+ * Write the given entry into the TLB at the given index.
+ * Pass full r4000 tlb info including variable page size mask.
+ *
+ * mipsN_TLBWriteIndexed(index, tlb)
+ * unsigned index;
+ * tlb *tlb;
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * TLB entry set.
+ *
+ *--------------------------------------------------------------------------
+ */
+ LEAF(MIPSX(TLBWriteIndexedVPS))
+ _MFC0 v1, MIPS_COP_0_STATUS # Save the status register.
+ _MTC0 zero, MIPS_COP_0_STATUS # Disable interrupts
+ nop
+ lw a2, 8(a1)
+ lw a3, 12(a1)
+ _MFC0 v0, MIPS_COP_0_TLB_PG_MASK # Save current page mask.
+ _MFC0 t0, MIPS_COP_0_TLB_HI # Save the current PID.
+
+ _MTC0 a2, MIPS_COP_0_TLB_LO0 # Set up entry low0.
+ _MTC0 a3, MIPS_COP_0_TLB_LO1 # Set up entry low1.
+ nop
+ lw a2, 0(a1)
+ lw a3, 4(a1)
+ nop
+ _MTC0 a0, MIPS_COP_0_TLB_INDEX # Set the index.
+ _MTC0 a2, MIPS_COP_0_TLB_PG_MASK # Set up entry mask.
+ _MTC0 a3, MIPS_COP_0_TLB_HI # Set up entry high.
+ nop
+ tlbwi # Write the TLB
+ nop
+ nop
+ nop # Delay for effect
+ nop
+
+ _MTC0 t0, MIPS_COP_0_TLB_HI # Restore the PID.
+ nop
+ _MTC0 v0, MIPS_COP_0_TLB_PG_MASK # Restore page mask.
+ j ra
+ _MTC0 v1, MIPS_COP_0_STATUS # Restore the status register
+ END(MIPSX(TLBWriteIndexedVPS))
+
+ /*--------------------------------------------------------------------------
+ *
* mipsN_TLBUpdate --
*
* Update the TLB if highreg is found; otherwise do nothing.
Index: sys/arch/mips/mips/mips3_wired_map.c
===================================================================
RCS file: sys/arch/mips/mips/mips3_wired_map.c
diff -N sys/arch/mips/mips/mips3_wired_map.c
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- sys/arch/mips/mips/mips3_wired_map.c 25 Oct 2005 20:39:56 -0000 1.1
***************
*** 0 ****
--- 1,176 ----
+ /* $NetBSD: wired_map.c,v 1.8 2005/01/22 07:35:33 tsutsui Exp $ */
+
+ /*-
+ * Copyright (c) 2005 Tadpole Computer Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Tadpole Computer Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Tadpole Computer Inc. may not be used to endorse
+ * or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+ /*
+ * Copyright (C) 2000 Shuichiro URATA. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*
+ * This code is derived from similiar code in the ARC port of NetBSD, but
+ * it now bears little resemblence to it owing to quite different needs
+ * from the mapping logic.
+ */
+
+ #include <sys/cdefs.h>
+ __KERNEL_RCSID(0, "$NetBSD$");
+
+ #include <sys/param.h>
+ #include <sys/systm.h>
+ #include <uvm/uvm_extern.h>
+ #include <machine/cpu.h>
+ #include <machine/locore.h>
+ #include <machine/pte.h>
+ #include <mips/wired_map.h>
+
+ static struct wired_map_entry {
+ paddr_t pa0;
+ paddr_t pa1;
+ vaddr_t va;
+ } wired_map[MIPS3_WIRED_ENTRIES];
+
+ static boolean_t mips3_wire_down_page(vaddr_t va, paddr_t pa);
+
+ static int nwired = 0;
+
+ boolean_t
+ mips3_wire_down_page(vaddr_t va, paddr_t pa)
+ {
+ struct tlb tlb;
+ int index;
+ int found = 0;
+
+ if ((va & MIPS3_WIRED_ENTRY_OFFMASK) ||
+ (pa & MIPS3_WIRED_ENTRY_OFFMASK))
+ panic("mips3_wire_down_page: not aligned");
+
+ for (index = 0; index < nwired; index++) {
+ if (wired_map[index].va == va) {
+ found++;
+ break;
+ }
+ }
+ if (found == 0) {
+ /* we have to allocate a new wired entry */
+ if (nwired >= MIPS3_WIRED_ENTRIES)
+ return 0;
+ index = nwired;
+ nwired++;
+
+ /* Allocate new wired entry */
+ mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES + nwired + 1);
+ }
+
+ /* record phys addresses */
+ wired_map[index].pa0 = pa;
+ wired_map[index].pa1 = pa + MIPS3_WIRED_PG_SIZE;
+ wired_map[index].va = va;
+
+ /* map it */
+ tlb.tlb_mask = MIPS3_WIRED_PG_MASK;
+ tlb.tlb_hi = mips3_vad_to_vpn(va);
+ if (wired_map[index].pa0 == 0)
+ tlb.tlb_lo0 = MIPS3_PG_G;
+ else
+ tlb.tlb_lo0 = mips3_paddr_to_tlbpfn(wired_map[index].pa0) | \
+ MIPS3_PG_IOPAGE(PMAP_CCA_FOR_PA(wired_map[index].pa0));
+ if (wired_map[index].pa1 == 0)
+ tlb.tlb_lo1 = MIPS3_PG_G;
+ else
+ tlb.tlb_lo1 = mips3_paddr_to_tlbpfn(wired_map[index].pa1) | \
+ MIPS3_PG_IOPAGE(PMAP_CCA_FOR_PA(wired_map[index].pa1));
+ MachTLBWriteIndexedVPS(MIPS3_TLB_WIRED_UPAGES + index, &tlb);
+ return 1;
+ }
+
+
+ /*
+ * Wire down pages. Returns the actual size wired down, as we may
+ * have to wire down more memory than that. In general, we always
+ * wire down 32 MB at a time, to simplify the logic. This means that
+ * mappings must always be on a 32MB boundary.
+ *
+ * Typically the caller will just pass a physaddr that is the same as
+ * the vaddr with bits 35-32 set nonzero.
+ */
+ boolean_t
+ mips3_wire_down(vaddr_t va, paddr_t pa, vsize_t size)
+ {
+ vaddr_t vend;
+ /*
+ * This routine allows for for wired mappings to be set up,
+ * and handles previously defined mappings and mapping
+ * overlaps reasonably well. However, caution should be used
+ * not to attempt to change the mapping for a page unless you
+ * are certain that you are the only user of the virtual
+ * address space, otherwise chaos may ensue.
+ */
+
+ /* offsets within the 32MB page have to be identical */
+ if ((va & MIPS3_WIRED_ENTRY_OFFMASK) !=
+ (pa & MIPS3_WIRED_ENTRY_OFFMASK))
+ panic("mips3_wire_down: mismatched offsets!");
+
+ vend = va + size;
+ /* adjust for alignment */
+ va &= ~MIPS3_WIRED_ENTRY_OFFMASK;
+ pa &= ~MIPS3_WIRED_ENTRY_OFFMASK;
+
+ while (va < vend) {
+ if (!mips3_wire_down_page(va, pa))
+ return 0;
+ va += MIPS3_WIRED_ENTRY_SIZE;
+ pa += MIPS3_WIRED_ENTRY_SIZE;
+ }
+ return 1;
+ }
Index: sys/arch/mips/include/locore.h
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/include/locore.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -c -r1.1.1.1 -r1.2
*** sys/arch/mips/include/locore.h 29 Sep 2005 16:42:49 -0000 1.1.1.1
--- sys/arch/mips/include/locore.h 24 Oct 2005 22:06:38 -0000 1.2
***************
*** 57,62 ****
--- 57,63 ----
void mips3_TBIS(vaddr_t);
int mips3_TLBUpdate(u_int, u_int);
void mips3_TLBRead(int, struct tlb *);
+ void mips3_TLBWriteIndexedVPS(u_int, struct tlb *);
void mips3_wbflush(void);
void mips3_proc_trampoline(void);
void mips3_cpu_switch_resume(void);
***************
*** 69,74 ****
--- 70,76 ----
void mips5900_TBIS(vaddr_t);
int mips5900_TLBUpdate(u_int, u_int);
void mips5900_TLBRead(int, struct tlb *);
+ void mips5900_TLBWriteIndexedVPS(u_int, struct tlb *);
void mips5900_wbflush(void);
void mips5900_proc_trampoline(void);
void mips5900_cpu_switch_resume(void);
***************
*** 83,88 ****
--- 85,91 ----
void mips32_TBIS(vaddr_t);
int mips32_TLBUpdate(u_int, u_int);
void mips32_TLBRead(int, struct tlb *);
+ void mips32_TLBWriteIndexedVPS(u_int, struct tlb *);
void mips32_wbflush(void);
void mips32_proc_trampoline(void);
void mips32_cpu_switch_resume(void);
***************
*** 95,100 ****
--- 98,104 ----
void mips64_TBIS(vaddr_t);
int mips64_TLBUpdate(u_int, u_int);
void mips64_TLBRead(int, struct tlb *);
+ void mips64_TLBWriteIndexedVPS(u_int, struct tlb *);
void mips64_wbflush(void);
void mips64_proc_trampoline(void);
void mips64_cpu_switch_resume(void);
***************
*** 228,233 ****
--- 232,238 ----
#define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries)
#define MIPS_TBIS mips3_TBIS
#define MachTLBUpdate mips3_TLBUpdate
+ #define MachTLBWriteIndexedVPS mips3_TLBWriteIndexedVPS
#define proc_trampoline mips3_proc_trampoline
#define wbflush() mips3_wbflush()
#elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64)
***************
*** 235,240 ****
--- 240,246 ----
#define MIPS_TBIAP() mips32_TBIAP(mips_num_tlb_entries)
#define MIPS_TBIS mips32_TBIS
#define MachTLBUpdate mips32_TLBUpdate
+ #define MachTLBWriteIndexedVPS mips32_TLBWriteIndexedVPS
#define proc_trampoline mips32_proc_trampoline
#define wbflush() mips32_wbflush()
#elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64)
***************
*** 243,248 ****
--- 249,255 ----
#define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries)
#define MIPS_TBIS mips64_TBIS
#define MachTLBUpdate mips64_TLBUpdate
+ #define MachTLBWriteIndexedVPS mips64_TLBWriteIndexedVPS
#define proc_trampoline mips64_proc_trampoline
#define wbflush() mips64_wbflush()
#elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900)
***************
*** 250,255 ****
--- 257,263 ----
#define MIPS_TBIAP() mips5900_TBIAP(mips_num_tlb_entries)
#define MIPS_TBIS mips5900_TBIS
#define MachTLBUpdate mips5900_TLBUpdate
+ #define MachTLBWriteIndexedVPS mips5900_TLBWriteIndexedVPS
#define proc_trampoline mips5900_proc_trampoline
#define wbflush() mips5900_wbflush()
#else
Index: sys/arch/mips/include/wired_map.h
===================================================================
RCS file: sys/arch/mips/include/wired_map.h
diff -N sys/arch/mips/include/wired_map.h
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- sys/arch/mips/include/wired_map.h 24 Oct 2005 22:06:38 -0000 1.1
***************
*** 0 ****
--- 1,87 ----
+ /* $NetBSD: wired_map.h,v 1.2 2005/01/22 07:35:33 tsutsui Exp $ */
+
+ /*-
+ * Copyright (c) 2005 Tadpole Computer Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Tadpole Computer Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Tadpole Computer Inc. may not be used to endorse
+ * or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TADPOLE COMPUTER INC.
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ #ifndef _MIPS_WIRED_MAP_H
+ #define _MIPS_WIRED_MAP_H
+
+ /*
+ * Certain machines have peripheral busses which are only accessible
+ * using the TLB.
+ *
+ * For example, certain Alchemy parts place PCI and PCMCIA busses at
+ * physical address spaces which are beyond the normal 32-bit range.
+ * In order to access these spaces TLB entries mapping 36-bit physical
+ * addresses to 32-bit logical addresses must be used.
+ *
+ * Note that all wired mappings are must be 32 MB aligned. This is
+ * because we use 32 MB mappings in the TLB. Changing this might get
+ * us more effficent use of the address space, but it would greatly
+ * complicate the code, and would also probably consume additional TLB
+ * entries.
+ *
+ * Note that within a single 32 MB region, you can have multiple
+ * decoders, but they must decode uniquely within the same 32MB of
+ * physical address space.
+ *
+ * BEWARE: The start of KSEG2 (0xC0000000) is used by the NetBSD kernel
+ * for context switching and is associated with wired entry 0. So you
+ * cannot use that, as I discovered the hard way.
+ *
+ * Note also that at the moment this is not supported on the MIPS-I
+ * ISA (but it shouldn't need it anyway.)
+ */
+ #define MIPS3_WIRED_PG_MASK MIPS3_PG_SIZE_16M /* 16 MB */
+ #define MIPS3_WIRED_PG_SIZE MIPS3_PG_SIZE_MASK_TO_SIZE(MIPS3_WIRED_PG_MASK)
+ #define MIPS3_WIRED_ENTRY_SIZE (MIPS3_WIRED_PG_SIZE * 2) /* 32 MB */
+ #define MIPS3_WIRED_ENTRY_OFFMASK (MIPS3_WIRED_ENTRY_SIZE - 1)
+
+ /*
+ * This defines the maximum number of wired TLB entries that the wired
+ * map will be allowed to consume. It can (and probably will!)
+ * consume fewer, but it will not consume more. Note that NetBSD also
+ * uses one wired entry for context switching (see TLB_WIRED_UPAGES),
+ * and that is not included in this number.
+ */
+ #ifndef MIPS3_WIRED_ENTRIES
+ #define MIPS3_WIRED_ENTRIES 8 /* upper limit */
+ #endif /* MIPS3_WIRED_ENTRIES */
+
+
+ /*
+ * Wire down a mapping from a virtual to physical address. Note that
+ * the size of the region must be a multiple of 32 MB (WIRED_ENTRY_SIZE)
+ * and the alignment must be on a 32 MB (WIRED_ENTRY_SIZE) boundary.
+ */
+ boolean_t mips3_wire_down(vaddr_t, paddr_t, vsize_t);
+
+ #endif /* _MIPS_WIRED_MAP_H */
Index: sys/arch/arc/arc/locore_machdep.S
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/arc/arc/locore_machdep.S,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -c -r1.1.1.2 -r1.2
*** sys/arch/arc/arc/locore_machdep.S 17 Oct 2005 16:48:16 -0000 1.1.1.2
--- sys/arch/arc/arc/locore_machdep.S 24 Oct 2005 22:06:38 -0000 1.2
***************
*** 332,385 ****
nop
END(mdbpanic)
#endif /* DEBUG */
-
- .set mips3
-
- /*--------------------------------------------------------------------------
- *
- * mips3_TLBWriteIndexedVPS --
- *
- * Write the given entry into the TLB at the given index.
- * Pass full r4000 tlb info including variable page size mask.
- *
- * mips3_TLBWriteIndexed(unsigned int index, struct tlb *tlb)
- *
- * Results:
- * None.
- *
- * Side effects:
- * TLB entry set.
- *
- *--------------------------------------------------------------------------
- */
- LEAF(mips3_TLBWriteIndexedVPS)
- mfc0 v1, MIPS_COP_0_STATUS # Save the status register.
- mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
- nop
- lw a2, 8(a1)
- lw a3, 12(a1)
- mfc0 v0, MIPS_COP_0_TLB_PG_MASK # Save current PageMask.
- dmfc0 t0, MIPS_COP_0_TLB_HI # Save the current PID.
-
- dmtc0 a2, MIPS_COP_0_TLB_LO0 # Set up EntryLo0.
- dmtc0 a3, MIPS_COP_0_TLB_LO1 # Set up EntryLo1.
- nop
- lw a2, 0(a1)
- lw a3, 4(a1)
- nop
- mtc0 a0, MIPS_COP_0_TLB_INDEX # Set the Index.
- mtc0 a2, MIPS_COP_0_TLB_PG_MASK # Set up PageMask.
- dmtc0 a3, MIPS_COP_0_TLB_HI # Set up EntryHi.
- nop
- tlbwi # Write the TLB
- nop
- nop
- nop # Delay for effect
- nop
-
- dmtc0 t0, MIPS_COP_0_TLB_HI # Restore the PID.
- nop
- mtc0 v0, MIPS_COP_0_TLB_PG_MASK # Restore PageMask.
- j ra
- mtc0 v1, MIPS_COP_0_STATUS # Restore the status register
- END(mips3_TLBWriteIndexedVPS)
--- 332,334 ----
Index: sys/arch/arc/include/cpu.h
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/arc/include/cpu.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -c -r1.1.1.1 -r1.2
*** sys/arch/arc/include/cpu.h 29 Sep 2005 16:38:20 -0000 1.1.1.1
--- sys/arch/arc/include/cpu.h 24 Oct 2005 22:06:38 -0000 1.2
***************
*** 20,28 ****
#define INT_MASK_REAL_DEV MIPS3_HARD_INT_MASK /* XXX */
- #ifndef _LOCORE
- struct tlb;
- extern void mips3_TLBWriteIndexedVPS(u_int index, struct tlb *tlb);
- #endif /* ! _LOCORE */
-
#endif /* _ARC_CPU_H_ */
--- 20,23 ----
--------------070803030002010104070804--