On Monday 07 March 2005 21:47, David Laight wrote:
>  - keep a count of the number of bytes written since the fifo was last
>    known to be empty.
>  - only enable the tx interrupt if there isn't space in the fifo for all
>    the data queued to be tr4ansmitted

In general that isn't going to buy you much, if anything.

>  - treat the TXRDY ISR value as an indication that the fifo is empty
>    (no reason to waste cpu cycles reading the LSR)

There was some further discussion on a Linux mailing list that this behavior 
can be problematic.  As I understand it, some chips clear the LSR when you 
write to the THR long before they clear the interrupt status, so in a number 
of situations (particularly with level-triggered interrupts) you can end up 
thinking you have another TXRDY interrupt.  Although I don't actually 
remember any more, this is probably why I implemented it using the LSR in the 
first place.

So, "it's not that simple".