On Mon, Mar 11, 2002 at 02:54:16PM -0800, Tad Hunt wrote:
> 
> The problem here is that according to the ATA spec, you're supposed to wait
> a certain length of time before reading the register.  On the order of 400 ns
> or so...

This is a tricky one!

For most command BUSY is set first, then later DRQ set and BUSY cleared.
So you can tell what has happened.

However if you issue a command that doesn't involve a data transfer,
it is somewhat harder to determine whether BUSY hasn't been set yet,
or has been set and then cleared.

I don't have the ATA spec handy - and can't remember if there
is anything that would tell you that a sector erase, for example,
had completed.

(For CF, I think performance would be inproved if the filesystem
code generated erase requests when sectors were no longer required,
this would give the device free sectors to play with.)

	David

-- 
David Laight: david@l8s.co.uk