> Well, the problem is that the ATA interface was never designed for shared
> interrupts: reading the status register will clear the pending interrupt,
> which opens the door to race condition. The ATA device is supposed to
> update the status register before posting the interrupt.
> For pciide devices this is solved by using status registers in the pciide
> device itself (which is vendor-specific, unfortunably). But for pcmcia/cardbus
> devices I can't see how we can solve this, unless there are vendor-specific
> registers where we could check for pending interrupt, designed to work in
> shared interrupt context.

What is wrong with the 'alternate' status register?
(returns the same as the status register but without
clearing the IRQ).

OTOH is is perfectly possible to write an ATA driver
that will never unintentionally clear an IRQ.

Also, the interrupt loop would be caused by FAILING to
remove an IRQ, not by removing one when it shouldn't be.

Maybe one if the ISRs is reporting that it 'used' the
interrupt when that wasn't the case.


	David

-- 
David Laight: david@l8s.co.uk