Subject: port-i386/11114: AMD750 Athlon chipset support for PCIBIOS_INTR_FIXUP
To: None <gnats-bugs@gnats.netbsd.org>
From: None <minoura@netbsd.org>
List: netbsd-bugs
Date: 10/01/2000 23:11:25
>Number: 11114
>Category: port-i386
>Synopsis: AMD750 Athlon chipset support for PCIBIOS_INTR_FIXUP
>Confidential: no
>Severity: serious
>Priority: medium
>Responsible: port-i386-maintainer
>State: open
>Class: change-request
>Submitter-Id: net
>Arrival-Date: Sun Oct 01 23:17:00 PDT 2000
>Closed-Date:
>Last-Modified:
>Originator: Minoura Makoto
>Release: 20000930
>Organization:
Minoura Makoto <minoura@netbsd.org> or <minoura@jp.netbsd.org>
>Environment:
System: NetBSD daisy 1.5G NetBSD 1.5G (DAISY) #168: Sun Oct 1 20:00:29 JST 2000 root@daisy:/usr/obj/sys/arch/i386/compile/DAISY i386
NetBSD 1.5G (DAISY) #168: Sun Oct 1 20:00:29 JST 2000
root@daisy:/usr/obj/sys/arch/i386/compile/DAISY
cpu0: AMD K7 (Athlon) (686-class)
cpu0: features 183f9ff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,SEP,MTRR>
cpu0: features 183f9ff<PGE,MCA,CMOV,FGPAT,PSE36,MMX,FXSR>
total memory = 127 MB
avail memory = 91172 KB
using 8150 buffers containing 32600 KB of memory
BIOS32 rev. 0 found at 0xfdb50
PCI BIOS rev. 2.1 found at 0xfdb71
PCI IRQ Routing Table rev. 1.0 found at 0xf7950, size 144 bytes (7 entries)
PCI Interrupt Router at 000:07:3 (Advanced Micro Devices AMD756 Power Management Controller)
mainbus0 (root)
[snip]
pcib0: Advanced Micro Devices AMD756 PCI-to-ISA Bridge (rev. 0x01)
[snip]
Advanced Micro Devices AMD756 Power Management Controller (miscellaneous bridge, revision 0x03) at pci0 dev 7 function 3 not configured
>Description:
PCIBIOS_INTR_FIXUP requires chipset-specific drivers.
Attached is the one for the Advanced Micro Devices AMD756
Peripheral Bus Controller (Viper), which composes the AMD750
chipset together with the AMD751 System Controller (Irongate).
B
>How-To-Repeat:
N/A
>Fix:
Index: sys/arch/i386/conf/files.i386
===================================================================
RCS file: /proj/CVSROOT/netbsd/src/sys/arch/i386/conf/files.i386,v
retrieving revision 1.1.1.15
retrieving revision 1.10
diff -u -r1.1.1.15 -r1.10
--- sys/arch/i386/conf/files.i386 2000/09/28 06:37:49 1.1.1.15
+++ sys/arch/i386/conf/files.i386 2000/10/02 05:46:08 1.10
@@ -137,6 +137,7 @@
file arch/i386/pci/opti82c700.c pcibios & pcibios_intr_fixup
file arch/i386/pci/sis85c503.c pcibios & pcibios_intr_fixup
file arch/i386/pci/via82c586.c pcibios & pcibios_intr_fixup
+file arch/i386/pci/amd756.c pcibios & pcibios_intr_fixup
file arch/i386/pci/pci_bus_fixup.c pcibios & pcibios_bus_fixup
file arch/i386/pci/pci_addr_fixup.c pcibios & pcibios_addr_fixup
defopt PCI_CONF_MODE
Index: sys/arch/i386/pci/amd756.c
===================================================================
RCS file: amd756.c
diff -N amd756.c
--- /dev/null Mon Oct 2 14:44:32 2000
+++ /tmp/cvs22469ac Mon Oct 2 14:47:22 2000
@@ -0,0 +1,259 @@
+/* $NetBSD$ */
+
+/*-
+ * Copyright (c) 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1999, by UCHIYAMA Yasushi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. The name of the developer may NOT be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Support for the Advanced Micro Devices AMD756 Peripheral Bus Controller.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <machine/intr.h>
+#include <machine/bus.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcidevs.h>
+
+#include <i386/pci/pci_intr_fixup.h>
+#include <i386/pci/amd756reg.h>
+
+struct viper_handle {
+ bus_space_tag_t ph_iot;
+ bus_space_handle_t ph_regs_ioh;
+ pci_chipset_tag_t ph_pc;
+ pcitag_t ph_tag;
+};
+
+int amd756_getclink __P((pciintr_icu_handle_t, int, int *));
+int amd756_get_intr __P((pciintr_icu_handle_t, int, int *));
+int amd756_set_intr __P((pciintr_icu_handle_t, int, int));
+int amd756_get_trigger __P((pciintr_icu_handle_t, int, int *));
+int amd756_set_trigger __P((pciintr_icu_handle_t, int, int));
+#ifdef VIPER_DEBUG
+static void amd756_pir_dump __P((struct viper_handle *));
+#endif
+
+const struct pciintr_icu amd756_pci_icu = {
+ amd756_getclink,
+ amd756_get_intr,
+ amd756_set_intr,
+ amd756_get_trigger,
+ amd756_set_trigger,
+};
+
+
+int
+amd756_init(pc, iot, tag, ptagp, phandp)
+ pci_chipset_tag_t pc;
+ bus_space_tag_t iot;
+ pcitag_t tag;
+ pciintr_icu_tag_t *ptagp;
+ pciintr_icu_handle_t *phandp;
+{
+ struct viper_handle *ph;
+
+ ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT);
+ if (ph == NULL)
+ return (1);
+
+ ph->ph_iot = iot;
+ ph->ph_pc = pc;
+ ph->ph_tag = tag;
+
+ *ptagp = &amd756_pci_icu;
+ *phandp = ph;
+
+#ifdef VIPER_DEBUG
+ amd756_pir_dump(ph);
+#endif
+
+ return 0;
+}
+
+int
+amd756_getclink(v, link, clinkp)
+ pciintr_icu_handle_t v;
+ int link, *clinkp;
+{
+ if (AMD756_LEGAL_LINK(link - 1) == 0)
+ return (1);
+
+ *clinkp = link - 1;
+ return (0);
+}
+
+int
+amd756_get_intr(v, clink, irqp)
+ pciintr_icu_handle_t v;
+ int clink, *irqp;
+{
+ struct viper_handle *ph = v;
+ pcireg_t reg;
+ int val;
+
+ if (AMD756_LEGAL_LINK(clink) == 0)
+ return (1);
+
+ reg = AMD756_GET_PIIRQSEL(ph);
+ val = (reg >> (4*clink)) & 0x0f;
+ *irqp = (val == 0) ?
+ I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
+
+ return (0);
+}
+
+int
+amd756_set_intr(v, clink, irq)
+ pciintr_icu_handle_t v;
+ int clink, irq;
+{
+ struct viper_handle *ph = v;
+ int val;
+ pcireg_t reg;
+
+ if (AMD756_LEGAL_LINK(clink) == 0 || AMD756_LEGAL_IRQ(irq) == 0)
+ return (1);
+
+ reg = AMD756_GET_PIIRQSEL(ph);
+ amd756_get_intr(v, clink, &val);
+ reg &= ~(0x000f << (4*clink));
+ reg |= irq << (4*clink);
+ AMD756_SET_PIIRQSEL(ph, reg);
+
+ return 0;
+}
+
+int
+amd756_get_trigger(v, irq, triggerp)
+ pciintr_icu_handle_t v;
+ int irq, *triggerp;
+{
+ struct viper_handle *ph = v;
+ int i, pciirq;
+ pcireg_t reg;
+
+ if (AMD756_LEGAL_IRQ(irq) == 0)
+ return (1);
+
+ for (i = 0; i <= 3; i++) {
+ amd756_get_intr(v, i, &pciirq);
+ if (pciirq == irq) {
+ reg = AMD756_GET_EDGESEL(ph);
+ if (reg & (1 << i))
+ *triggerp = IST_EDGE;
+ else
+ *triggerp = IST_LEVEL;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int
+amd756_set_trigger(v, irq, trigger)
+ pciintr_icu_handle_t v;
+ int irq, trigger;
+{
+ struct viper_handle *ph = v;
+ int i, pciirq;
+ pcireg_t reg;
+
+ if (AMD756_LEGAL_IRQ(irq) == 0)
+ return (1);
+
+ for (i = 0; i <= 3; i++) {
+ amd756_get_intr(v, i, &pciirq);
+ if (pciirq == irq) {
+ reg = AMD756_GET_PIIRQSEL(ph);
+ if (trigger == IST_LEVEL)
+ reg &= ~(1 << (4*i));
+ else
+ reg |= 1 << (4*i);
+ AMD756_SET_PIIRQSEL(ph, reg);
+ break;
+ }
+ }
+
+ return (0);
+}
+
+#ifdef VIPER_DEBUG
+static void
+amd756_pir_dump(ph)
+ struct viper_handle *ph;
+{
+ int a, b;
+
+ printf ("VIPER PCI INTERRUPT ROUTING REGISTERS:\n");
+
+ a = AMD756_GET_EDGESEL(ph);
+ b = AMD756_GET_PIIRQSEL(ph);
+
+ printf ("TRIGGER: %02x, ROUTING: %04x\n", a, b);
+}
+#endif
Index: sys/arch/i386/pci/amd756reg.h
===================================================================
RCS file: amd756reg.h
diff -N amd756reg.h
--- /dev/null Mon Oct 2 14:44:32 2000
+++ /tmp/cvs22469ad Mon Oct 2 14:47:22 2000
@@ -0,0 +1,75 @@
+/* $NetBSD$ */
+
+/*
+ * Copyright (c) 1999, by UCHIYAMA Yasushi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. The name of the developer may NOT be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Register definitions for the AMD756 Peripheral Bus Controller.
+ */
+
+/*
+ * Edge Triggered Interrupt Select register. (0x54)
+ * bits 7-4: reserved
+ * bit 3: Edge Triggered Interrupt Select for PCI Interrupt D
+ * bit 2: Edge Triggered Interrupt Select for PCI Interrupt C
+ * bit 1: Edge Triggered Interrupt Select for PCI Interrupt B
+ * bit 0: Edge Triggered Interrupt Select for PCI Interrupt A
+ * 0 = active Low and level triggered
+ * 1 = active High and edge triggered
+ *
+ * PIRQ Select register. (0x56-57)
+ * bits 15-12: PIRQD# Select
+ * bits 11-8: PIRQD# Select
+ * bits 7-4: PIRQD# Select
+ * bits 3-0: PIRQD# Select
+ * 0000: Reserved 0100: IRQ4 1000: Reserved 1100: IRQ12
+ * 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved
+ * 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14
+ * 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15
+ */
+#define AMD756_CFG_PIR 0x54
+
+#define AMD756_GET_EDGESEL(ph) \
+ (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \
+ & 0xff)
+
+#define AMD756_GET_PIIRQSEL(ph) \
+ (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \
+ >> 16)
+
+#define AMD756_SET_EDGESEL(ph, n) \
+ pci_conf_write((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR, \
+ (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \
+ & 0xffff0000) | (n))
+
+#define AMD756_SET_PIIRQSEL(ph, n) \
+ pci_conf_write((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR, \
+ (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \
+ & 0x000000ff) | ((n) << 16))
+
+#define AMD756_PIRQ_MASK 0xdefa
+#define AMD756_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3)
+#define AMD756_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
+ ((1 << (irq)) & AMD756_PIRQ_MASK) != 0)
Index: sys/arch/i386/pci/pci_intr_fixup.c
===================================================================
RCS file: /proj/CVSROOT/netbsd/src/sys/arch/i386/pci/pci_intr_fixup.c,v
retrieving revision 1.1.1.5
retrieving revision 1.2
diff -u -r1.1.1.5 -r1.2
--- sys/arch/i386/pci/pci_intr_fixup.c 2000/08/17 00:31:27 1.1.1.5
+++ sys/arch/i386/pci/pci_intr_fixup.c 2000/10/02 05:46:08 1.2
@@ -147,6 +147,9 @@
{ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503,
sis85c503_init },
+ { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC756_PMC,
+ amd756_init },
+
{ 0, 0,
NULL },
};
Index: sys/arch/i386/pci/pci_intr_fixup.h
===================================================================
RCS file: /proj/CVSROOT/netbsd/src/sys/arch/i386/pci/pci_intr_fixup.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- sys/arch/i386/pci/pci_intr_fixup.h 1999/11/17 01:20:38 1.1.1.1
+++ sys/arch/i386/pci/pci_intr_fixup.h 2000/10/02 05:46:08 1.2
@@ -63,3 +63,5 @@
pciintr_icu_tag_t *, pciintr_icu_handle_t *));
int sis85c503_init __P((pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
pciintr_icu_tag_t *, pciintr_icu_handle_t *));
+int amd756_init __P((pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
+ pciintr_icu_tag_t *, pciintr_icu_handle_t *));
>Release-Note:
>Audit-Trail:
>Unformatted: