>Number:         5249
>Category:       port-mips
>Synopsis:       mips3_ConfigCache generates wrong cache sizes
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    gnats-admin (GNATS administrator)
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Thu Apr  2 22:05:01 1998
>Last-Modified:
>Originator:     Noriyuki Shiota
>Organization:
Ricoh Co., Ltd.
>Release:        NetBSD-current
>Environment:
original port based on NetBSD-pmax
>Description:
	mips3_ConfigCache extracts inst/data cache size from config register.
	But the two bit field extracted from config register are completely
	reverse. Inst cache size has been stored in mips_L1DataCacheSize,
	data cache size has been stored in mips_L1InstCacheSize.
>How-To-Repeat:
	Read mips3_ConfigCache code.
>Fix:
--- sys/arch/mips/mips/locore_r4000.S	1998/01/14 00:25:09	1.1
+++ sys/arch/mips/mips/locore_r4000.S	1998/03/25 01:59:10
@@ -1625,29 +1855,29 @@
  */
 LEAF(mips3_ConfigCache)
 	mfc0	v0, MIPS_COP_0_CONFIG		# Get configuration register
 	nop
-	srl	t1, v0, 9			# Get D cache size.
+	srl	t1, v0, 6			# Get D cache size.
 	and	t1, 7				# ???
 	li	t2, 4096
 	sllv	t2, t2, t1
 	sw	t2, mips_L1DataCacheSize
 	addiu	t2, -1
 	and	t2, ~(NBPG - 1)
 	sw	t2, mips_CacheAliasMask
 
-	and	t2, v0, 0x20
-	srl	t2, t2, 1
+	and	t2, v0, 0x10
 	addu	t2, t2, 16
 	sw	t2, mips_L1DataCacheLSize
 
-	srl	t1, v0, 6			# Get I cache size.
+	srl	t1, v0, 9			# Get I cache size.
 	and	t1, 7				# ???
 	li	t2, 4096
 	sllv	t2, t2, t1
 	sw	t2, mips_L1InstCacheSize
 
-	and	t2, v0, 0x10
+	and	t2, v0, 0x20
+	srl	t2, t2, 1
 	addu	t2, t2, 16
 	sw	t2, mips_L1InstCacheLSize
 
 	lui	t1, 2
>Audit-Trail:
>Unformatted: