>Number:         2574
>Category:       kern
>Synopsis:       Computer hangs when attempting 2nd connection to ISP with pppd
>Confidential:   no
>Severity:       critical
>Priority:       medium
>Responsible:    kern-bug-people (Kernel Bug People)
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Wed Jun 26 23:50:01 1996
>Last-Modified:
>Originator:     Clifford Wright
>Organization:
	
>Release:        1.1
>Environment:
	
	486DX4 with US Robotics 28.8 fax modem with 16550-compatible UART
System: NetBSD vixen 1.1 NetBSD 1.1 (VIXEN) #28: Tue Jun 25 01:40:06 PDT 1996 cliff@vixen:/usr/src/sys/arch/i386/compile/VIXEN i386


>Description:
	
	This problem related directly to NetBSD Problem Report #1042.
	Under various combinations of modem use the machine would hang.

>How-To-Repeat:
	
	I was always able to repeat the problem when reconnecting to my
	Internet Service Provider.

>Fix:
	
	After examining the patch indicated in NetBSD Problem Report #1042,
	it appeared that the code did not follow the comments. After reording
	the patch code the patch solved my problem. The diff to base NetBSD
	1.1 follows.

*** com.c.orig	Fri Oct 13 19:38:23 1995
--- com.c	Tue Jun 25 01:39:25 1996
***************
*** 311,321 ****
  		sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE;
  
  		iobase = sc->sc_iobase;
! 		/* Set the FIFO threshold based on the receive speed. */
! 		if (sc->sc_hwflags & COM_HW_FIFO)
! 			outb(iobase + com_fifo,
! 			    FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
! 			    (tp->t_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
  		/* flush any pending I/O */
  		while (inb(iobase + com_lsr) & LSR_RXRDY)
  			(void) inb(iobase + com_data);
--- 311,341 ----
  		sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE;
  
  		iobase = sc->sc_iobase;
! 		if (sc->sc_hwflags & COM_HW_FIFO) {
! 			/*
! 			 * (Re)enable and drain FIFOs.
! 			 *
! 			 * Certain SMC chips cause problems if the FIFOs are
! 			 * enabled while input is ready. Turn off the FIFO
! 			 * if necessary to clear the input. Test the input
! 			 * ready bit after enabling the FIFOs to handle races
! 			 * between enabling and fresh input.
! 			 *
! 			 * Set the FIFO threshold based on the receive speed.
! 			 */
! 			 for (;;) {
! 				outb(iobase + com_fifo, 0);
! 				delay(100);
! 				(void) inb(iobase + com_data);
! 				outb(iobase + com_fifo,
! 			    	FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
! 			    	(tp->t_ispeed <= 1200 ?
! 			    	FIFO_TRIGGER_1 : FIFO_TRIGGER_8));
! 				delay(100);
! 				if((inb(iobase + com_lsr) & LSR_RXRDY) == 0)
! 					break;
! 			}
! 		}
  		/* flush any pending I/O */
  		while (inb(iobase + com_lsr) & LSR_RXRDY)
  			(void) inb(iobase + com_data);
>Audit-Trail:
>Unformatted: