>Number:         1829
>Category:       port-amiga
>Synopsis:       grf_cv problems with new CV64 boards
>Confidential:   no
>Severity:       serious
>Priority:       high
>Responsible:    gnats-admin (GNATS administrator)
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Sat Dec  9 14:20:01 1995
>Last-Modified:
>Originator:     Matthias Scheler
>Organization:
Matthias Scheler
tron@colwyn.owl.de
>Release:        NetBSD-1.1
>Environment:
	
System: NetBSD 1.1 (LYSSA) #1: Sat Dec  9 18:51:53 GMT 1995 tron@lyssa:/usr/src/sys/arch/amiga/compile/LYSSA

>Description:
grf_cv cause bus errors with new boards of the CV64 due to a change in
the used S3 Trio chipset.

>How-To-Repeat:
Boot NetBSD-1.1 on a machine with such a board. It will crash while probing
the cards memory size.

>Fix:
*** src/sys/arch/amiga/dev/grf_cv.c.orig	Sat Nov 11 13:31:38 1995
--- src/sys/arch/amiga/dev/grf_cv.c	Sat Dec  9 19:50:44 1995
***************
*** 395,404 ****
  
  	clockpar = compute_clock(0x3473BC0);
  	test = (clockpar & 0xFF00) >> 8;
- 	WSeq(ba, SEQ_ID_MCLK_HI, test);		/* PLL N-Divider Value */
  
! 	test = clockpar & 0xFF;
! 	WSeq(ba, SEQ_ID_MCLK_LO, test);		/* PLL M-Divider Value */
  
  	/* We now load an 25 MHz, 31 kHz, 640x480 standard VGA Mode. */
  	/* DCLK */
--- 395,415 ----
  
  	clockpar = compute_clock(0x3473BC0);
  	test = (clockpar & 0xFF00) >> 8;
  
! 	if (RCrt(ba, CRT_ID_REVISION) == 0x10) {
! 		WSeq(ba, SEQ_ID_MCLK_HI, test);	/* PLL N-Divider Value */
! 
! 		test = clockpar & 0xFF;
! 		WSeq(ba, SEQ_ID_MCLK_LO, test);	/* PLL M-Divider Value */
! 
! 		test = (clockpar & 0xFF00) >> 8;
! 		WSeq(ba, SEQ_ID_MORE_MAGIC, test);
! 	} else {
! 		WSeq(ba, SEQ_ID_MCLK_HI, test);	/* PLL N-Divider Value */
! 
! 		test = clockpar & 0xFF;
! 		WSeq(ba, SEQ_ID_MCLK_LO, test);	/* PLL M-Divider Value */
! 	}
  
  	/* We now load an 25 MHz, 31 kHz, 640x480 standard VGA Mode. */
  	/* DCLK */

*** src/sys/arch/amiga/dev/grf_cvreg.h.orig	Sat Nov 11 13:31:39 1995
--- src/sys/arch/amiga/dev/grf_cvreg.h	Sat Dec  9 19:49:01 1995
***************
*** 158,163 ****
--- 158,164 ----
  #define SEQ_ID_CLKSYN_TEST_HI	0x16	/* reserved for S3 testing of the */
  #define SEQ_ID_CLKSYN_TEST_LO	0x17	/*   internal clock synthesizer   */
  #define SEQ_ID_RAMDAC_CNTL	0x18
+ #define SEQ_ID_MORE_MAGIC	0x1A
  
  /* CRT Controller: */
  #define CRT_ADDRESS		0x03D4
>Audit-Trail:
>Unformatted: