Subject: New kernel and patches
To: None <macbsd-development@pain.lcs.mit.edu>
From: Allen 'Time?' Briggs <briggs@puma.bevd.blacksburg.va.us>
List: macbsd-development
Date: 11/03/1994 07:29:34
The problem with serial not working with 1.0 kernels on the IIsi has
been fixed.  Enclosed are the patches from the README.late file that
is now on cray and will go on sun-lamp when I catch it when it's up.

These patches are applied to the latest netbsd10.patched kernel.

-allen

===========================+  Cut here  +===========================
A few patches for locore.s.
*** 1.19.2.3
--- sys/arch/mac68k/mac68k/locore.s
***************
*** 119,122 ****
--- 119,125 ----
  
  	.text
+ 	.space	(4096-1024)
+ 	.space	4096
+ 
  /*
   * This is where we wind up if the kernel jumps to location 0.
***************
*** 935,939 ****
  
  | MMU is on; if not '030, then just turn it off
! 	tstl	_mmutype		| ttx instructions will break 68851
  	jne	Lnoremap		| not '030 -- skip all this
  
--- 938,942 ----
  
  | MMU is on; if not '030, then just turn it off
! 	cmpl	#MMU_68030,_mmutype
  	jne	Lnoremap		| not '030 -- skip all this
  
***************
*** 1329,1333 ****
  | LAK: Kill the TT0 and TT1 registers so the don't screw us up later.
  	tstl	_mmutype		| ttx instructions will break 68851
! 	jne	LnokillTT
  	lea	longscratch,a0
  	movl	#0, a0@
--- 1332,1336 ----
  | LAK: Kill the TT0 and TT1 registers so the don't screw us up later.
  	tstl	_mmutype		| ttx instructions will break 68851
! 	jgt	LnokillTT
  	lea	longscratch,a0
  	movl	#0, a0@
***************
*** 2523,2527 ****
  	movc	d0,cacr			| disable on-chip cache(s)
  
! 	tstl	_mmutype
  	jeq	Lmap030rom		| don't turn off MMU if '030
  
--- 2526,2530 ----
  	movc	d0,cacr			| disable on-chip cache(s)
  
! 	cmpl	#MMU_68030,_mmutype
  	jeq	Lmap030rom		| don't turn off MMU if '030
  
===================================================================
A patch for grf.c from monroe@cs.pdx.edu.
*** 1.7.2.2
--- sys/arch/mac68k/dev/grf.c
***************
*** 545,549 ****
  	gi->gd_dwidth=gi->gd_fbwidth=image->right;
  	gi->gd_dheight=gi->gd_fbheight=image->bottom;
! 	gi->gd_fbsize=image->right*image->bottom;
  	gi->gd_fbrowbytes=image->rowbytes;
  	gi->gd_fbaddr=(caddr_t) ((u_long)image->offset+(u_long)nu->addr);
--- 545,549 ----
  	gi->gd_dwidth=gi->gd_fbwidth=image->right;
  	gi->gd_dheight=gi->gd_fbheight=image->bottom;
! 	gi->gd_fbsize=image->rowbytes*image->bottom;
  	gi->gd_fbrowbytes=image->rowbytes;
  	gi->gd_fbaddr=(caddr_t) ((u_long)image->offset+(u_long)nu->addr);
====================================================================
A patch so that the IIsi can use the serial ports again.
*** sys/arch/mac68k/dev/ser.c.orig
--- sys/arch/mac68k/dev/ser.c
***************
*** 146,155 ****
  	12, 0x04,	/* time constant LB. */
  	13, 0x00,	/* time constant HB. */
! 	14, 0x82,	/* miscellaneous control.  Bit d0 (BR gen enable)
  			   must be set to 0 at this time. */
  	 3, 0xc1,	/* set d0 (rx enable). */
  	 5, 0xea,	/* set d3 (tx enable). */
  	 0, 0x80,	/* reset txCRC. */
! 	14, 0x83,	/* BR gen enable.  Enable DPLL. */
  	 1, 0x00,	/* make sure DMA not set. */
  	15, 0x00,	/* disable external interrupts. */
--- 146,155 ----
  	12, 0x04,	/* time constant LB. */
  	13, 0x00,	/* time constant HB. */
! 	14, 0x00,	/* miscellaneous control.  Bit d0 (BR gen enable)
  			   must be set to 0 at this time. */
  	 3, 0xc1,	/* set d0 (rx enable). */
  	 5, 0xea,	/* set d3 (tx enable). */
  	 0, 0x80,	/* reset txCRC. */
! 	14, 0x01,	/* BR gen enable.  Enable DPLL. */
  	 1, 0x00,	/* make sure DMA not set. */
  	15, 0x00,	/* disable external interrupts. */
***************
*** 193,198 ****
  			ser_init_bytes[i+1] = ((spd>>8) & 0xff);
  		if (!running_interrupts) {
! 			if (   ser_init_bytes[i]   == 0x00
! 			    && ser_init_bytes[i+1] == 0x10)
  				break;
  		}
--- 193,198 ----
  			ser_init_bytes[i+1] = ((spd>>8) & 0xff);
  		if (!running_interrupts) {
! 			if (   ser_init_bytes[i]   == 0x01
! 			    && ser_init_bytes[i+1] == 0x0a)
  				break;
  		}
===========================+  Cut here  +===========================