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If you have a TI PCI1420 PCI-CardBus bridge, will you try the patch I have
attached?  See if it improves transmit performance for your CardBus NICs.
It's best if you test using a 100 or 1000 Mb/s ethernet NIC.

You need to apply the patch to -current of a few hours ago.

Your dmesg may identify your PCI1420 bridge like this,

cbb0 at pci0 dev 17 function 0: vendor 0x104c product 0xac51 (rev. 0x00)
cbb1 at pci0 dev 17 function 1: vendor 0x104c product 0xac51 (rev. 0x00)

Dave

-- 
David Young             OJC Technologies
dyoung@ojctech.com      Urbana, IL * (217) 278-3933 ext 24

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? .pccbb.c.swp
Index: pccbb.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pccbb.c,v
retrieving revision 1.147
diff -p -u -u -p -r1.147 pccbb.c
--- pccbb.c	11 Aug 2007 00:45:35 -0000	1.147
+++ pccbb.c	11 Aug 2007 01:15:46 -0000
@@ -317,7 +317,7 @@ const struct yenta_chipinfo {
 	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
 	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX,
 	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
-	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX,
+	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420,
 	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
 	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X,
 	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
@@ -815,6 +817,16 @@ pccbb_chipinit(struct pccbb_softc *sc)
 		pci_conf_write(pc, tag, PCI_CBCTRL, cbctl);
 		break;
 
+	case CB_TI1420:
+		sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL);
+		if ((sysctrl & PCI1420_SYSCTRL_MRBURST) !=
+		    PCI1420_SYSCTRL_MRBURST) {
+			printf("%s: enabling read bursts\n",
+			    device_xname(&sc->sc_dev));
+			sysctrl |= PCI1420_SYSCTRL_MRBURST;
+			pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl);
+		}
+		/*FALLTHROUGH*/
 	case CB_TI12XX:
 		/*
 		 * Some TI 12xx (and [14][45]xx) based pci cards
Index: pccbbreg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pccbbreg.h,v
retrieving revision 1.12
diff -p -u -u -p -r1.12 pccbbreg.h
--- pccbbreg.h	11 Aug 2007 00:31:05 -0000	1.12
+++ pccbbreg.h	11 Aug 2007 01:15:46 -0000
@@ -131,6 +131,13 @@
 #define PCI12XX_CBCTRL_SPK_ENA 0x0200 /* Speaker enable */
 #define PCI12XX_CBCTRL_INTR_DET 0x0100 /* functional interrupt detect */
 
+/* 1: permit burst read from CardBus (default: on) */
+#define	PCI1420_SYSCTRL_MRBURSTON	__BIT(15)
+/* 1: permit burst read from PCI bus (default: off!) */
+#define	PCI1420_SYSCTRL_MRBURSTUP	__BIT(14)
+
+#define	PCI1420_SYSCTRL_MRBURST	\
+	(PCI1420_SYSCTRL_MRBURSTON|PCI1420_SYSCTRL_MRBURSTUP)
 
 /* PCI_BCR_INTR additional bit for Rx5C46[567] */
 #define CB_BCRI_RL_3E0_ENA 0x08000000

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