Subject: Re: NVIDIA nForce2/3/4 SMBus controller
To: None <blymn@baesystems.com.au>
From: KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
List: current-users
Date: 07/03/2007 16:07:59
Hi!, blymn
From: Brett Lymn <blymn@baesystems.com.au>
Date: Mon, 2 Jul 2007 11:45:37 +0930
> On Sun, Jul 01, 2007 at 06:14:46PM +0900, KIYOHARA Takashi wrote:
> >
> > For instance, two registers of slaveaddr and read/write are used in
> > nfsmb(4). However, amdpm(4) is set to one register. Moreover, there
> > is no register like 'host start' of amdpm(4).
> > You should read {amdpm_smbus,nfsmb}_{send,write,receive,read}_1().
> >
>
> OK - but it does seem strange to me we have two drivers that do almost
> the same thing. How about setting up the send/write/receive/read
> operations in the softc and selecting the correct set when the chip is
> probed/attached?
I don't understand the meaning of your question. ;-<
Which is it nfsmb_softc or nfsmbc_softc? And, the operation of adt7463
selects nfsmb_softc to which iic(4) is appropriate for instance.
--
kiyohara