Subject: Re: NVIDIA nForce2/3/4 SMBus controller
To: None <,>
From: KIYOHARA Takashi <>
List: current-users
Date: 07/01/2007 18:14:46
Hi! Bernd  and  blymn,

From: Brett Lymn <>
Date: Sun, 1 Jul 2007 16:20:19 +0930

> On Sun, Jul 01, 2007 at 08:12:52AM +0200, Bernd Ernesti wrote:
> > 
> > I added the attached patch to amdpm where I ended up with:
> > 
> Yes, I did very much the same thing with amdpm.c (I think your code is
> nicer though :) on my nforce4 board and I get:
> amdpm0 at pci0 dev 1 function 1: NVIDIA nForce4 SMBus (rev. 0xa2)
> amdpm_smbus_attach...
> LSMB: Picked IRQ 20 with weight 0
> linkdev LSMB returned ACPI global int 20
> amdpm0: interrupting at ioapic0 pin 20 (irq 0)
> iic0 at amdpm0: I2C bus
> amdpm0: random number generator enabled (apprx. 0ms)

As for amdpm(4) and nfsmb(4), the register is different.  You will not
merge these. 

For instance, two registers of slaveaddr and read/write are used in
nfsmb(4).  However, amdpm(4) is set to one register.  Moreover, there
is no register like 'host start' of amdpm(4). 
You should read {amdpm_smbus,nfsmb}_{send,write,receive,read}_1().