Subject: Re: VIA C7 CPU and crypto capabilities SOLVED partially
To: Juan RP <>
From: Heron Gallegos <>
List: current-users
Date: 06/30/2007 21:50:02

I am ready to test your patches:

On Sat, 30 Jun 2007, Heron Gallegos wrote:

>>> #define CPUVENDOR_UNKNOWN       -1
>>> #define CPUVENDOR_INTEL         0
>>> #define CPUVENDOR_CYRIX         1
>>> #define CPUVENDOR_NEXGEN        2
>>> #define CPUVENDOR_AMD           3
>>> #define CPUVENDOR_IDT           4
>>> #define CPUVENDOR_TRANSMETA     5
>> #define CPUVENDOR_VIA 8

C3 and C7 chips use CPUVENDOR_IDT as cpu_vendor in identcpu.c

>> Let me know if that works and I'll commit.
> if I have previous initialized ACE, rdmsr returns 0x100400,
> if not, then rdmsr returns 0x110400 and I got the message:
> cpu0: unknown Enhanced SpeedStep CPU

ACE was initialized at start up the CPU (CPUID_VIA_DO_ACE)
I supose the problem was when it was initialized the second
time, Now I dont loose TM2 and SpeedStep.

I have tested the patches with the following modification:

                 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) {
                         if (cpu_vendor == CPUVENDOR_INTEL)
                         if (cpu_vendor == CPUVENDOR_IDT)
                 } else
                         aprint_normal("%s: Enhanced SpeedStep disabled by

and I have this output:

cpu0: using thermal monitor 2
cpu0: Enhanced SpeedStep (1004 mV) 533 MHz
cpu0: unknown Enhanced SpeedStep CPU.
cpu0: using only highest, current and lowest power states.
cpu0: Enhanced SpeedStep frequencies available (MHz): 667 533 533
cpu0: calibrating local timer

The cpu is marked as "unknown", but it is in the list of
x86/x86/est.c C7M_770_ULV

Thanks again, Juan
Also Thanks to Christos Zoulas and Daniel De Kok

Heron Gallegos
Saltillo Coahuila Mexico