In article <Pine.NEB.4.64.0706282017510.29887@antares.csxxi.sepc.edu.mx>,
Heron Gallegos  <gallegos@csxxi.net.mx> wrote:
>On Tue, 26 Jun 2007, Daniel de Kok wrote:
>
>> Could you try the attached patch against sys/arch/i386/i386/identcpu.c?
>Thanks, Daniel
>Also I did some modification to identcpu.c
>
>identcpu.c now can find the capabilities [Centaur Extended Feature Flags]
>but now I have loose TM2 and SpeedStep.
>------------------------------------------------------------
>polaris# diff dmesg1 dmesg2
>7c7
>< NetBSD 4.99.20 (POLARIS) #23: Thu Jun 28 19:46:12 CDT 2007
>---
>> NetBSD 4.99.20 (POLARIS) #25: Thu Jun 28 21:38:38 CDT 2007
>17c17
>< cpu0: VIA C3 (686-class), 799.98 MHz, id 0x6a9
>---
>> cpu0: VIA C7 Esther (686-class), 799.99 MHz, id 0x6a9
>27,31c27,29
>< cpu0: using thermal monitor 2
>< cpu0: Enhanced SpeedStep (1004 mV) 533 MHz
>< cpu0: unknown Enhanced SpeedStep CPU.
>< cpu0: using only highest, current and lowest power states.
>< cpu0: Enhanced SpeedStep frequencies available (MHz): 667 533 533
>---
>> cpu0: enabling thermal monitor 1 ... failed!
>> cpu0: failed to enable thermal monitoring!
>> cpu0: Enhanced SpeedStep disabled by BIOS
>175a174
>> PadLock: registered support for AES_CBC
>polaris#
>------------------------------------------------------------------------------
>polaris# diff /sys/arch/i386/i386/identcpu.c.orig /sys/arch/i386/i386/identcpu.c
>483c483
><                               "C3 Nehemiah", 0, 0, 0, 0, 0, 0,
>---
>>                               "C3 Nehemiah", "C7 Esther", 0, 0, 0, 0, 0,
>666c666,670
><               /* Nehemiah or Esther */
>---
>>               /*
>>                * Nehemiah model 9 [RNG, ACE]
>>                * Esther model 10 (0xa) [RNG, ACE, ACE2, PHE, PMM]
>>                * 
>http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
>>                */
>669,670c673,674
><               if (lfunc == 0xc0000001) {
><                       CPUID(lfunc, descs[0], descs[1], descs[2], descs[3]);
>---
>>               if (lfunc >= 0xc0000001) {
>>                       CPUID(0xc0000001, descs[0], descs[1], descs[2], 
>descs[3]);
>polaris#
>-------------------------------------------------------

Can you try this, and let us know what it prints... I have not even
compile-tested it but it should be close.

christos

Index: i386/i386/identcpu.c
===================================================================
RCS file: /cvsroot/src/sys/arch/i386/i386/identcpu.c,v
retrieving revision 1.67
diff -u -u -r1.67 identcpu.c
--- i386/i386/identcpu.c	19 Jun 2007 14:16:56 -0000	1.67
+++ i386/i386/identcpu.c	29 Jun 2007 16:49:39 -0000
@@ -480,7 +480,7 @@
 			{
 				0, 0, 0, 0, 0, 0, "C3 Samuel",
 				"C3 Samuel 2/Ezra", "C3 Ezra-T",
-				"C3 Nehemiah", 0, 0, 0, 0, 0, 0,
+				"C3 Nehemiah", "C7 Esther", 0, 0, 0, 0, 0,
 				"C3"	/* Default */
 			},
 			NULL,
@@ -666,12 +666,14 @@
 		/* Nehemiah or Esther */
 		CPUID(0xc0000000, descs[0], descs[1], descs[2], descs[3]);
 		lfunc = descs[0];
-		if (lfunc == 0xc0000001) {
-			CPUID(lfunc, descs[0], descs[1], descs[2], descs[3]);
+		if (lfunc >= 0xc0000001) {
+			CPUID(0xc0000001, descs[0], descs[1], descs[2],
+			    descs[3]);
 			lfunc = descs[3];
 			if (model > 0x9 || stepping >= 8) {	/* ACE */
-				if ((lfunc & 0xc0) == 0xc0) {
-					ci->ci_padlock_flags |= CPUID_FEAT_VACE;
+				ci->ci_padlock_flags = lfunc;
+#define VIA_ACE 	(CPUID_VIA_HAS_ACE|CPUID_VIA_DO_ACE)
+				if ((lfunc & VIA_ACE)  == VIA_ACE) {
 					msr = rdmsr(MSR_VIA_ACE);
 					wrmsr(MSR_VIA_ACE,
 					    msr | MSR_VIA_ACE_ENABLE);
@@ -1468,6 +1470,12 @@
 		aprint_verbose("%s: features3 %s\n", cpuname, buf);
 	}
 
+	if (ci->ci_padlock_flags) {
+		bitmask_snprintf(ci->ci_padlock_flags,
+			CPUID_FLAGS_PADLOCK, buf, MAXPATHLEN);
+		aprint_verbose("%s: padlock features %s\n", cpuname, buf);
+	}
+
 	free(buf, M_TEMP);
 
 	if (*cpu_brand_string != '\0')
Index: x86/include/specialreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/include/specialreg.h,v
retrieving revision 1.16
diff -u -u -r1.16 specialreg.h
--- x86/include/specialreg.h	4 Jun 2007 16:21:29 -0000	1.16
+++ x86/include/specialreg.h	29 Jun 2007 16:49:39 -0000
@@ -155,11 +155,20 @@
 				    "\0373DNOW2\0403DNOW"
 
 /*
- * "Features" that are copied from elsewhere -- not necessarily tied to
- * a specific CPUID response
+ * Centaur Extended Feature flags
  */
+#define CPUID_VIA_HAS_RNG	0x00000004	/* Random number generator */
+#define CPUID_VIA_DO_RNG	0x00000008
+#define CPUID_VIA_HAS_ACE	0x00000040	/* AES Encryption */
+#define CPUID_VIA_DO_ACE	0x00000080
+#define CPUID_VIA_HAS_ACE2	0x00000100	/* AES+CTR instructions */
+#define CPUID_VIA_DO_ACE2	0x00000200
+#define CPUID_VIA_HAS_PHE	0x00000400	/* SHA1+SHA256 HMAC */
+#define CPUID_VIA_DO_PHE	0x00000800
+#define CPUID_VIA_HAS_PMM	0x00001000	/* RSA Instructions */
+#define CPUID_VIA_DO_PMM	0x00002000
 
-#define CPUID_FEAT_VACE	0x00000002	/* VIA C3 AES Crypto Extension */
+#define CPUID_FLAGS_PADLOCK	"\20\3RNG\7AES\11AES/CTR\13SHA1/SHA256\15RSA"
 
 /*
  * CPUID "features" bits in %ecx
Index: x86/x86/via_padlock.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/via_padlock.c,v
retrieving revision 1.4
diff -u -u -r1.4 via_padlock.c
--- x86/x86/via_padlock.c	21 Mar 2007 23:24:58 -0000	1.4
+++ x86/x86/via_padlock.c	29 Jun 2007 16:49:39 -0000
@@ -57,7 +57,8 @@
 void
 via_padlock_attach(void)
 {
-	if (!(cpu_feature_padlock & CPUID_FEAT_VACE))
+#defne VIA_ACE (CPUID_VIA_HAS_PADLOCK|CPUID_VIA_DO_PADLOCK)
+	if ((cpu_feature_padlock & VIA_ACE) != VIA_ACE)
 		return;
 
 	struct via_padlock_softc *vp_sc;