On Saturday 17 March 2007, Juan RP wrote:
> Hi,
>
> I'm posting patches for review and test. The patches do:
>
> * Implement two new IPI handlers: IPI_READ_MSR and IPI_WRITE_MSR.
> * To read or write a MSR in all CPUs (x86_broadcast_ipi(IPI_READ_MSR)).
> * Provide two functions for the drivers to read and write MSRs with IPIs,
> passing a struct pointer:
>
> struct msr_cpu_broadcast {
> 	int msr_type;	/* MSR type, e.g MSR_PERF_CTL, MSR_THERM_CONTROL... */
> 	uint64_t msr_value;	/* MSR value passed to the write function */
> };
>
> /* Reads a MSR in all CPUs */
> msr_cpu_broadcast_read(struct msr_cpu_broadcast *);
>
> /* Writes a value in MSR define in msr_type in all CPUs */
> msr_cpu_broadcast_write(struct msr_cpu_broadcast *);
>
> I tested with p4tcc, and it seems to work. If you have Enhanced Speedstep
> running in a Core Duo (or SMP compatible), please test the patches and
> show me debug output (it's enabled by default).
>
> I can do the patches for POWERNOW_K8, just let me know that and I'll do.
>
> http://www.netbsd.org/~xtraeme/msr_ipi_handlers.diff
> http://www.netbsd.org/~xtraeme/est_smp.diff

I made the patch for POWERNOW_K8, it's untested but it should work.

http://www.netbsd.org/~xtraeme/powernow_k8_smp.diff

Please test!

p4tcc works perfectly (debugging output confirms that):

$ sysctl -w machdep.p4tcc.throttling.target=7

msr_cpu_broadcast_write: msr=0

msr_cpu_broadcast: ---- START ----
msr_cpu_broadcast: before write
msr_cpu_broadcast: after write
msr_write_ipi: (cpu0) before write
msr_cpu_broadcast: before pause
msr_write_ipi: (cpu0) after write
msr_cpu_broadcast: x86_msr_runcount=2 ncpu=2
msr_write_ipi: (cpu1) before write
msr_cpu_broadcast: after pause
msr_write_ipi: (cpu1) after write
cpu0: ci_msr_rvalue=0x30
cpu1: ci_msr_rvalue=0x30
msr_cpu_broadcast: ----- END -----

As you can see, same MSR value was written in all CPUs available
on the system. YAY.

-- 

http://plog.xtrarom.org/
Juan RP's blog - NetBSD/pkgsrc news in Spanish