On Jan 22, 2007, at 11:31 AM, Havard Eidnes wrote:
>>    Please let me know if the earlier patch can be committed.  =20
>> Thank you.
>
> In view of my own lack of expertise in this area, I'll hold off
> on answering that one for the time being, though my guess is that
> it's probably a "yes".
>
> Meanwhile, I've adapted your patch to -current, foldet to 80
> coloumns, and added a comment -- diff attached.

   Thanks.  One small note.  It's >=3D "stepping" C0, which is revision =20=

0x03.  Changing either word in the comment you added would make it =20
less confusing.

   Thanks much!

                 - Chris

>
> Regards,
>
> - H=E5vard
> Index: pchb.c
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> RCS file: /cvsroot/src/sys/arch/i386/pci/pchb.c,v
> retrieving revision 1.62
> diff -u -r1.62 pchb.c
> --- pchb.c	16 Nov 2006 01:32:39 -0000	1.62
> +++ pchb.c	22 Jan 2007 16:28:58 -0000
> @@ -194,23 +194,31 @@
>  			break;
>  		case PCI_PRODUCT_INTEL_82443BX_AGP:
>  		case PCI_PRODUCT_INTEL_82443BX_NOAGP:
> -			/*
> -			 * BIOS BUG WORKAROUND!  The 82443BX
> -			 * datasheet indicates that the only
> -			 * legal setting for the "Idle/Pipeline
> -			 * DRAM Leadoff Timing (IPLDT)" parameter
> -			 * (bits 9:8) is 01.  Unfortunately, some
> -			 * BIOSs do not set these bits properly.
> -			 */
> -			bcreg =3D pci_conf_read(pa->pa_pc, pa->pa_tag,
> -			    I82443BX_SDRAMC_REG);
> -			if ((bcreg & 0x0300) !=3D 0x0100) {
> -				aprint_verbose("%s: fixing Idle/Pipeline =
DRAM "
> -				    "Leadoff Timing\n", self->dv_xname);
> -				bcreg &=3D ~0x0300;
> -				bcreg |=3D  0x0100;
> -				pci_conf_write(pa->pa_pc, pa->pa_tag,
> -				    I82443BX_SDRAMC_REG, bcreg);
> +		/*
> +		 * =
http://www.intel.com/design/chipsets/specupdt/290639.htm
> +		 * says this bug is fixed in revisions >=3D C0 (erratum =
11),
> +		 * so don't tweak the bits in that case.
> +		 */
> +			if (PCI_REVISION(pa->pa_class) <=3D 0x02) {
> +				/*
> +				 * BIOS BUG WORKAROUND!  The 82443BX
> +				 * datasheet indicates that the only
> +				 * legal setting for the "Idle/Pipeline
> +				 * DRAM Leadoff Timing (IPLDT)" =
parameter
> +				 * (bits 9:8) is 01.  Unfortunately, =
some
> +				 * BIOSs do not set these bits properly.
> +				 */
> +				bcreg =3D pci_conf_read(pa->pa_pc, =
pa->pa_tag,
> +				    I82443BX_SDRAMC_REG);
> +				if ((bcreg & 0x0300) !=3D 0x0100) {
> +					aprint_verbose("%s: fixing "
> +					    "Idle/Pipeline DRAM "
> +					    "Leadoff Timing\n", =
self->dv_xname);
> +					bcreg &=3D ~0x0300;
> +					bcreg |=3D  0x0100;
> +					pci_conf_write(pa->pa_pc, =
pa->pa_tag,
> +					    I82443BX_SDRAMC_REG, bcreg);
> +				}
>  			}
>  			break;
>