Subject: Re: SpeedStep problem
To: None <email@example.com>
From: Juan RP <firstname.lastname@example.org>
Date: 09/08/2006 00:52:34
On Thu, 7 Sep 2006 16:20:04 +0200
Juan RP <email@example.com> wrote:
> On Wed, 6 Sep 2006 01:20:40 +0200
> Kurt Schreiner <firstname.lastname@example.org> wrote:
> > Hi,
> > since some days Enhanced SpeedStep doesn't work anymore on my IBM
> > T43p; dmesg output from -current (some minutes "old") look's like
> > this:
> > cpu0 at mainbus0: apid 0 (boot processor)
> > cpu0: Intel Pentium M (Dothan) (686-class), 2128.35 MHz, id 0x6d8
> > cpu0: features
> > afe9fbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR> cpu0:
> > features afe9fbff<PGE,MCA,CMOV,PAT,CFLUSH,DS,ACPI,MMX> cpu0:
> > features afe9fbff<FXSR,SSE,SSE2,SS,TM,SBF> cpu0: features2
> > 180<EST,TM2> cpu0: "Intel(R) Pentium(R) M processor 2.13GHz"
> > cpu0: I-cache 32 KB 64B/line 8-way, D-cache 32 KB 64B/line 8-way
> > cpu0: L2 cache 2 MB 64B/line 8-way
> > cpu0: using thermal monitor 2
> > cpu0: Enhanced SpeedStep (1356 mV) 2133 MHz
> > cpu0: unknown Enhanced SpeedStep CPU.
> > cpu0: using only highest and lowest power states.
> > cpu0: Enhanced SpeedStep frequencies available (MHz): 2133 800
> > cpu0: calibrating local timer
> > cpu0: apic clock running at 133 MHz
> > cpu0: 64 page colors
> For some reason the table is being skipped and idlo is wrong,
> atm the problem is unknown.
> I'm working on it...
Looks like the table was wrong until now:
Module Name: src
Committed By: xtraeme
Date: Thu Sep 7 22:50:50 UTC 2006
- Fix Pentium M 770 table. I don't know why did work before but
the values were not correct... tested by seb@.
- Remove binary bits from struct fqlist members, why do we need them?
To generate a diff of this commit:
cvs rdiff -r1.26 -r1.27 src/sys/arch/i386/i386/est.c
Can you please test to see if that fixes the problem for you too?